• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.851-856
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• 2003

We have investigated the material and electrical properties of $Bi_{4-x}La_xTi_3O_{12}$ (BLT) ferroelectric thin film for ferroelectric nonvolatile memory applications of capacitor type and single transistor type. The 120nm thick BLT films were deposited on $Pt/Ti/SiO_2/Si$ and $SiO_2/Nitride/SiO_2$ (ONO) substrates by the sol-gel spin coating method and were annealed at $700^{\circ}C$. It was observed that the crystallographic orientation of BLT thin films were strongly affected by the excess Bi content and the intermediate rapid thermal annealing (RTA) treatment conditions regardeless of two type substrates. However, the surface microstructure and roughness of BLT films showed dependence of two different type substrates with orientation of (111) plane and amorphous phase. As increase excess Bi content, the crystallographic orientation of the BLT films varied drastically in BLT films and exhibited well-crystallized phase. Also, the conversion of crystallographic orientation at intermediate RTA temperature of above $450^{\circ}C$ started to be observed in BLT thin films with above excess 6.5% Bi content and the rms roughness of films is decreased. We found that the electrical properties of BLT films such as the P-V hysteresis loop and leakage current were effectively modulated by the crystallographic orientations change of thin films.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.363-363
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• 2014

Ruthenium (Ru) has attractive material properties due to its promising characteristics such as a low resistivity ($7.1{\mu}{\Omega}{\cdot}cm$ in the bulk), a high work function of 4.7 eV, and feasibility for the dry etch process. These properties make Ru films appropriate for various applications in the state-of-art semiconductor device technologies. Thus, it has been widely investigated as an electrode for capacitor in the dynamic random access memory (DRAM), a metal gate for metal-oxide semiconductor field effect transistor (MOSFET), and a seed layer for Cu metallization. Due to the continuous shrinkage of microelectronic devices, better deposition processes for Ru thin films are critically required with excellent step coverages in high aspect ratio (AR) structures. In these respects, atomic layer deposition (ALD) is a viable solution for preparing Ru thin films because it enables atomic-scale control of the film thickness with excellent conformality. A recent investigation reported that the nucleation of ALD-Ru film was enhanced considerably by using a zero-valent metallorganic precursor, compared to the utilization of precursors with higher metal valences. In this study, we will present our research results on the synthesis and characterization of novel ruthenium complexes. The ruthenium compounds were easy synthesized by the reaction of ruthenium halide with appropriate organic ligands in protic solvent, and characterized by NMR, elemental analysis and thermogravimetric analysis. The molecular structures of the complexes were studied by single crystal diffraction. ALD of Ru film was demonstrated using the new Ru metallorganic precursor and O2 as the Ru source and reactant, respectively, at the deposition temperatures of $300-350^{\circ}C$. Self-limited reaction behavior was observed as increasing Ru precursor and O2 pulse time, suggesting that newly developed Ru precursor is applicable for ALD process. Detailed discussions on the chemical and structural properties of Ru thin films as well as its growth behavior using new Ru precursor will be also presented.

• Applied Chemistry for Engineering
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• v.19 no.4
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• pp.407-412
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• 2008

As an activation procedure, in this study, the oxidation treatment of needle cokes with a dilute nitric acid and sodium chlorate $(NaClO_3)$, combined with heat treatment, was attempted. The structures of acid-treated and pyrolyzed coke were examined with XRD, FESEM, elemental analyzer, BET, and Raman spectroscopy. The behavior of double layer capacitance was investigated with the analysis of charge and discharge. The structure of needle coke treated with acid was revealed to a single phase of (001) diffraction peak after 24 h. On the other hand, thecoke oxidized by heat treatment was reduced to a graphite structure of (002) at $300^{\circ}C$. The distorted graphene layer structure, derived from the process of oxidation and reduction of the inter-layer, makes the pores by the electric field activation at the first charge, and generates the double layer capacitance from the second charge. The cell using pyrolyzed coke with 24 h acid treatment and $300^{\circ}C$ heat treatment exhibited the maximum capacitance per weight and volume of 33 F/g and 30 F/mL at the two-electrode system in the potential range of 0~2.5 V.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.6
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• pp.709-718
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• 2017

The installation of the elevator ARD(Automatic Rescue Device) system has been forced into law in these days in order to safely rescue passengers during power failure. The configuration of the ARD system consists of energy storage device, power converter and control systems. The EDLC(Electric Double Layer Capacitor) are used as energy storage device for rapid charge/discharge purposes. The power conditioning system (PCS) consists of bi-directional converter, 3-phase converter and control system. The dead-beat control system is adopted for most systems however it requires complex mathematical calculations, the high performance microprocessors are mandatory and thus it can be a cause of high manufacturing cost. In this paper the new control method for average current mode control is presented for simple structure. The control algorithm is applied to the single phase system and then expands to three phase system to meet the sysem requirements. The mathematical modeling using average modeling method is presented and analysed by PSIM computer simulation to verifie the validity of the proposed control methods.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.