• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.343-346
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• 2010

We have investigated growth of CdTe thin films by using (As, GaAs) buffer layers for application of large scale IR focal plane arrays(IFPAs). Buffer layers were grown by molecular beam epitaxy(MBE), which reduced the lattice mismatch of CdTe/Si and prevented native oxide on Si substrates. CdTe thin films were grown by metal organic chemical deposition system(MOCVD). As a result, polycrystalline CdTe films were grown on Si(100) and arsenic coated-Si(100) substrate. In other case, single crystalline CdTe(400) thin film was grown on GaAs coated-Si(100) substrate. Moreover, we observed hillock structure and mirror like surface on the (400) orientated epitaxial CdTe thin film.

• Progress in Superconductivity
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• v.3 no.1
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• pp.125-129
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• 2001

NiO buffer layers were deposited on texture Ni tapes fur YBCO coated conductors by MOCVD(metal organic chemical vapor deposition) method, using a single solution source. Variables were deposition temperature and flow rate of $0_2$carrier gas. At higher temperatures, The NiO(111) texture was well developed, but the NiO(200) texture was developed at low temperatures. The best result was obtained at the deposition temperature of$ 470^{\circ}C$ and the gas flow rate of 200 sccm. FWHM value of $\omega$-scan fur NiO(200) of the film and $\Phi$-scan for NiO(111) of the film was $4.2^{\circ}$ and $7^{\circ}$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.125-130
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• 2000

Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.

• Nuclear Engineering and Technology
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• v.53 no.3
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• pp.1041-1048
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• 2021

An engineered barrier system (EBS) for the disposal of high-level radioactive waste (HLW) is composed of a disposal canister with spent fuel, a buffer material, a gap-filling material, and a backfill material. As the buffer is located in the empty space between the disposal canisters and the surrounding rock mass, it prevents the inflow of groundwater and retards the spill of radionuclides from the disposal canister. Due to the fact that the buffer gradually becomes saturated over a long time period, it is especially important to investigate its thermal-hydro-mechanical-chemical (THMC) properties considering variations of saturated condition. Therefore, this paper suggests a new method of measuring thermal conductivity and water suction for single compacted bentonite at various levels of saturation. This paper also highlights a convenient method of saturating compacted bentonite. The proposed method was verified with a previous method by comparing thermal conductivity and water suction with respect to water content. The relative error between the thermal conductivity and water suction values obtained through the proposed method and the previous method was determined as within 5% for compacted bentonite with a given water content.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• Transactions on Electrical and Electronic Materials
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• v.13 no.4
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• pp.208-211
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• 2012

In the present study, a ZnO thin film, as a buffer layer of ITO (indium tin oxide) film was deposited on glass substrates by RF magnetron sputtering at low temperature of $150^{\circ}C$. In order to estimate the optical characteristics and compare with the experimental results in Glass/ZnO(100 nm)/ITO(35 nm) multilayered film, the simulation program, EMP (Essential Macleod Program) was adopted. The sheet resistance and optical transmittance of the films were measured using the four-point probe method and spectrophotometer, respectively. From X-ray diffraction patterns, all the films deposited at $150^{\circ}C$ demonstrated only the amorphous phase. Optical transmittance was the highest at a ZnO thickness of 100 nm. The ITO(35 nm)/ZnO(100 nm) film exhibits an optical transmittance of >92% at 550 nm. The multilayered film showed an electrical sheet resistance of 407 ${\Omega}/sq.$, which is significantly better than that of a single-layer ITO film without a ZnO buffer layer (815 ${\Omega}/sq.$).

• Journal of the Korean Ceramic Society
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• v.34 no.4
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• pp.373-379
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• 1997

A study on the deposition and characterization of BaTiO3 thin films on MgO-buffered Si(100) substrates by sputtering was conducted. The MgO buffer layers were investigated as a function of deposition temperature. At lower substrate temperature, the MgO layers were not fully crystalline, but a crystallized MgO layer with (001) preferred orientation was obtained at the substrate temperature of $700^{\circ}C$. Partially (00ι) or (h00) textured BaTiO3 films were obtained on Si(100) with the MgO buffer layer grown at 700ι. While, randomly oriented BaTiO3 films with large-scale cracks on the surface were made without the MgO layer. The crystallographic orientation, morphology and electrical properties between the BaTiO3 films on Si with and without the MgO layer were compared using the BaTiO3 film on MgO(100) single crystal substrate as a reference system. Also the favorable role of the MgO layer as a buffer for growing of oriented BaTiO3 films on Si substrates was confirmed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.277-278
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• 2005

Admittance Spectroscopic analysis was applied to study the effect of LiF buffer layer and to model the equivalent circuit for poly(2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV)-based polymer light emitting diodes (PLEDs) with the LiF cathode buffer layer. The single layer device with ITO/MEH-PPV/Al structure can be modeled as a simple parallel combination of resistor and capacitor. Insertion of a LiF layer at the Al/MEH-PPV interface shifts the highest occupied molecular orbital level and the vacuum level of the MEH-PPV layer as a result the barrier height for electron injection at the Al/MEH-PPV interface is reduced. The admittance spectroscopy measurement of the devices with the LiF cathode buffer layer shows reduction in contact resistance ($R_c$), parallel resistance ($R_p$) and increment in parallel capacitance ($C_p$).

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.30-40
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• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1646-1648
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• 2000

This paper investigated structural and electrical properties of $Y_{2}O_3$ as a buffer layer of sin91r transistor FRAM (ferroelectric RAM). $Y_{2}O_3$ buffer layers were deposited at a low substrate temperature below 400$^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post- annealing temperature, and suppression of interfacial $SiO_2$ layer generation. for a well-fabricated sample, we achieved that leakage current density ($J_{leak}$) in the order of $10^{-7}A/cm2$, breakdown electric field ($E_{br}$) about 2 MV/cm for $Y_{2}O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_{2}O_3$/Si as low as $8.72{\times}10^{10}cm^{-2}eV^{-1}$. The low interface states were obtained from very low lattice mismatch less than 1.75%.