• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.51-56
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• 2003

We describe a charge pump circuit using VCO (voltage controlled oscillator) for storing information into local memories in neural networks. The VCO is used for adjusting the output voltage of the charge pump to the reference voltage and for reducing the fluctuation generated by the clocking scheme. The charge pump circuit is simulated by using Hynix 0.35um CMOS process parameters. The proposed charge pump operates properly regardless to the temperature and the supply voltage variation.

• Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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• 2002.04a
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• pp.148-154
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• 2002

Groundwater Dam is one of the reliable techniques to get huge amount of groundwater abstraction for municipal, agricultural, drinking, industrial water supply system. It can be a major technique to solve water shortage problems when it based on the sufficient watershed, proper topology, and adequate aquifer distribution and pollution control. It is suggested that the two consecutive underground wall in the coastal area to prevent seawater intrusion beneath a single wall.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.11a
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• pp.334-337
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• 2003

In this paper we presents a centralized model for a long-term replenishment contract model in the supply chain system. We assume ARIMA demand process for reflecting more realistic demand data and present a solution which minimizes total system cost of the contract model between single supplier and buyer under centralized system. From the result of experiments we can observe that the proposed model generate better result than the decentralized model.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.45-48
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• 2001

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.986-989
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• 1999

An 12bit current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current - mode multiplied folding amplifier is employed not only to reduced the number of reference current source, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The simulation result shows the power dissipation of 280㎽ with a power supply of 5V.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.149-153
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• 1999

As VLSI technology advances rapidly, the operating frequency of digital systems becomes very fast. In such a high-speed system, there are many factors that threaten signal integrity. The noise sources in digital system include the noises in power supply, ground bounce and packaging media and distortions on single and multiple transmission lines. This paper will present a technology survey useful in the design of Gigabit interconnection systems. Some case studies have been constructed which show the lossy transmission line effect of skin effect. dielectric loss, with backplane connectors using the theoretical and practical conditions.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.87-90
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• 2002

This paper describes design technique of switched-capacitor 1V delta-sigma modulator. To solve the incomplete switching operation at low voltage, bootstrapping technique is used. For PMOS input pair of 1V operational amplifier, simple common mode level down technique is used. Designed 2nd order single loop modulator has an oversampling ratio of 64 and obtains a peak SNR of 71dB, a dynamic range of 73 dB with the power consumption of 350uW at 1V power supply.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.941-944
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• 2000

This paper proposes, for the first time, the design of class I pull-push power amplifier. With the new design, the output power is increased by four times when compared to conventional single-end class I connection amplifier with the same supply voltage. The performance of the proposed amplifier is verified by with a 100-kHz power amplifier constructed using general-purpose NPN transistors.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.67-68
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• 2015

본 논문에서는 멀티모듈 단상 UPS(Uninterruptible Power Supply) 시스템의 예측 제어기법을 제안한다. 제안한 예측 제어기법은 단상 UPS의 수학적 모델링을 통해 설계되었으며, 전류 예측제어를 통해 모드 절환 시 동특성을 향상시켰다. 제안하는 예측 제어기법은 PSIM 시뮬레이션을 통하여 검증하였다.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1030-1034
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• 1993

A converter topology which is capable of four-quadrant(motoring and generation) operation is proposed for the variable speed constant frequency(hereafter referred as VSCF) power conversion scheme. The new converter topology for the VSCF power conversion scheme is made of two functional stages. One is converting stage which consists of six switches and six diodes and it interfaces a three-phase 60Hz at supply and a single-phase variable-frequency ac source. The other is the commutating stage though which each phase-winding is energized.