• Journal of Power Electronics
• /
• v.12 no.4
• /
• pp.623-631
• /
• 2012

In this paper, a digital controller design procedure is presented for single-phase voltage-doubler boost rectifiers (VDBR). The model derivation of the single-phase VDBR is performed in the s-domain. After that the simplified equivalent z-domain models are derived. These z-domain models are utilized to design the input current and the output dc-link voltage controllers. For the controller design in the z-domain, the traditional K-factor method is modified by considering the nature of the digital controller. The frequency pre-warping and anti-windup techniques are adapted for the controller design. By using the proposed method, the phase margin and the control bandwidth are accurately achieved as required by controller designers in a practical frequency range. The proposed method is applied to a 2.5 kVA single-phase VDBR for Uninterruptible Power Supply (UPS) applications. From the simulation and the experimental results, the effectiveness of the proposed design method has been verified.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.57-60
• /
• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• ETRI Journal
• /
• v.38 no.2
• /
• pp.217-226
• /
• 2016

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of $0.098mm^2$ and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-of-merit of the modulator is 191 fJ/conversion-step.

• Journal of Sensor Science and Technology
• /
• v.29 no.1
• /
• pp.68-73
• /
• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.21 no.1
• /
• pp.58-64
• /
• 2016

This study presents a design method for a single-loop voltage controller that is suitable for an arbitrary waveform generator (AWG). The voltage control algorithm of AWG should ensure high dynamic performance and should attain sufficient robustness to disturbances such as inverter nonlinearity, sensor noise, and load current. By analyzing the power circuit of AWG, control limitation and control target are presented to improve the dynamic performance of AWG. The proposed voltage control algorithm is composed of a single-loop output voltage control, an inverter current feedback term to improve transient response, and a load current feedforward term to prevent voltage distortion. The guideline for setting control gain is presented based on output filter parameters and digital time delay. The performance of the proposed algorithm is proven by experimental results through comparison with the conventional algorithm.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.53 no.2
• /
• pp.114-122
• /
• 2004

This paper presents a novel single-stage active-clamp type high frequency resonant inverter. The proposed topology is integrated full-bridge boost rectifier as power factor corrector and active-clamp type high frequency resonant inverter into a single-stage. The input stage of the full-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. By adding additional active-clamp circuit to conventional class-E high frequency resonant inverter, main switch of inverter part operates not only at Zero-Voltage-Switching mode but also reduces the switching voltage stress of main switch. Simulation results have demonstrated the feasibility of the proposed high frequency resonant inverter. Characteristics values based on characteristics estimation through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in the fields of induction heating applications, fluorescent lamp and DC-DC converter etc.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.54 no.12
• /
• pp.601-608
• /
• 2005

This paper presents a novel single-stage high-power-factor electronic ballast for fluorescent lamps operating in critical conduction mode. The proposed topology is based on integration of boost converter as power factor corrector(PFC) and a half-bridge high frequency parallel resonant inverter into a single stage. The input stage of the boost converter is operating in critical conduction mode for positive and negative half cycle voltage respectively at line frequency(60Hz). So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. The simulated and experimental results for 100W fluorescent lamps operating at 42kHz switching frequency and 220V line voltage have been obtained. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, fluorescent lamp and DC-DC converter etc.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.908-911
• /
• 1993

The single-Phase induction motor is widely used in many light duty applications. especially in home and the office. At present, many applications which use these motor require continuously adjustable speed control. In the general, the speed control of single-phase induction motor is accomplished at a few discrete speeds by using tapped-windings, pole switching or gear. These techniques is inefficient and complicated. In this paper, auxiliary winding voltage phase angle of single-phase induction motor is used to continuously adjust electromagnetic torque. The analysis includes the determination of the relationship between the auauxiliary winding voltage phase angle and torque. Simulation results of the motor's torque-speed characteristics using the controlled auxiliary winding supply are shown and discussed. The drive is tested using a dynamometer to experimentally verify the results of the theory and simulations.

• International journal of advanced smart convergence
• /
• v.10 no.1
• /
• pp.12-23
• /
• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• International Journal of Internet, Broadcasting and Communication
• /
• v.15 no.3
• /
• pp.122-128
• /
• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.