• 한국통신학회논문지
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• 제41권9호
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• pp.1095-1102
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• 2016

본 논문에서는 single parity check 부호(SPC)를 포함하는 3차원 turbo product 부호(TPC)의 효율적인 복호 기법을 제안한다. 일반적으로 TPC의 부호율을 극대화하기 위한 목적으로 부호 길이가 짧은 축에서 SPC 부호를 적용한다. 그러나 SPC 부호가 오류 정정 능력이 없는 부호이기 때문에 3차원 TPC를 Chase-Pyndiah 복호 알고리즘만으로 복호할 경우, 2차원 TPC에 비하여 성능 개선이 거의 발생하지 않는다. 본 논문에서는 이를 개선하기 위해 다음의 2가지 기법을 복호 과정에 적용하였다. 우선 SPC 부호로 이루어진 축에서는 구현 복잡도를 낮추기 위하여 $min^*$-sum 알고리즘을 복호 방법으로 적용하였으며, 반복 복호 방식으로는 성능 개선을 위해 직렬 복호 방식을 변형한 방식을 이용하였다. 마지막으로 이를 적용한 TPC 시뮬레이터의 성능을 비교 분석하고, 실제 하드웨어 구현과정에서 고려해야 할 부분을 소개한 후, VHDL을 이용하여 3차원 TPC를 설계하였다.

• Journal of Communications and Networks
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• 제11권5호
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• pp.455-463
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• 2009

We consider the challenges of finding good puncturing patterns for rate-compatible low-density parity-check code (LDPC) codes over additive white Gaussian noise (AWGN) channels. Puncturing is a scheme to obtain a series of higher rate codes from a lower rate mother code. It is widely used in channel coding but it causes performance is lost compared to non-punctured LDPC codes at the same rate. Previous work, considered the role of survived check nodes in puncturing patterns. Limitations, such as single survived check node assumption and simulation-based verification, were examined. This paper analyzes the performance according to the role of multiple survived check nodes and multiple dead check nodes. Based on these analyses, we propose new algorithm to find a good puncturing pattern for LDPC codes over AWGN channels.

• ETRI Journal
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• 제46권3호
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• ETRI Journal
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• 제31권5호
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• pp.518-524
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• 2009

Single parity check (SPC) product codes are simple yet powerful codes that are used to correct errors and/or recover erasures. The focus of this paper is to evaluate the performance of such codes under erasure scenarios and to develop a closed-form tight upper bound for the post-decoding erasure rate. Closed-form exact expressions are derived for up to seven erasures. Previously published closed-form bounds assumed that all unrecoverable patterns should contain four erasures in a square. Additional non-square patterns are accounted for in the proposed expressions. The derived expressions are verified using exhaustive search. Eight or more erasures are accounted for by using a bound. The developed expressions improve the evaluation of the recoverability of SPC product codes without the need for simulation or search algorithms, whether exhaustive or novel.

• 한국통신학회논문지
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• 제35권9C호
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• pp.721-728
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• 2010

재귀적 구조의 SPCPC (single parity check product code)인 CAMC (constant amplitude multi-code) 는 반복적 복호를 행할 때 SPCPC에 비하여 오류 정정 성능이 우수하다. 본 논문에서는 대역확산 신호인 CAMC의 처리 이득이 성능 향상에 미치는 영향을 분석한다. 일반적인 곱 부호에서는 반복적 복호로 오류 정정 과정이 종료되지만, CAMC 는 반복적 복호 후의 역확산 과정에서 추가적으로 오류가 정정된다. 잔존하는 비트 오류의 수가 ($\sqrt{N}/2-1$)개 이하인 경우에는 (N은 코드워드의 길이), 역확산 과정에서 그 오류들은 모두 정정된다. 반복적 복호에서 EI (extrinsic information)의 분포 형태를 관찰한 결과, 초기의 EI 분포는 대체로 랜덤하나, 몇 회의 iteration 후에는 ($-E_{max}$) 혹은 ($+E_{max}$)의 이진 값으로 수렴한다. EI의 분포가 오류 정정의 진행 사항을 반영하는 점을 이용하는 iteration 제어 방법을 실험한 결과 Eb/No 에서 약 0.2 dB의 이득을 얻었다.

• Journal of Communications and Networks
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• 제17권4호
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• pp.351-361
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• 2015

In this paper, a new decoding scheme is proposed to improve the error correcting performance of low-density parity-check (LDPC) codes in high signal-to-noise ratio (SNR) region by using post-processing. It behaves as follows: First, a conventional LDPC decoding is applied to received LDPC codewords one by one. Then, we count the number of word errors in a predetermined number of decoded codewords. If there is no word error, nothing needs to be done and we can move to the next group of codewords with no delay. Otherwise, we perform a proper post-processing which produces a new soft-valued codeword (this will be fully explained in the main body of this paper) and then apply the conventional LDPC decoding to it again to recover the unsuccessfully decoded codewords. For the proposed decoding scheme, we adopt a simple product code structure which contains LDPC codes and simple algebraic codes as its horizontal and vertical codes, respectively. The decoding capability of the proposed decoding scheme is defined and analyzed using the parity-check matrices of vertical codes and, especially, the combined-decodability is derived for the case of single parity-check (SPC) codes and Hamming codes used as vertical codes. It is also shown that the proposed decoding scheme achieves much better error correcting capability in high SNR region with little additional decoding complexity, compared with the conventional LDPC decoding scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.331-340
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• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.55-58
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• 2004

This this paper, we propose vertical Bell laboratories layered space time (V-BLAST) system based on variable rate Low-Density Parity Check (LDPC) codes to improve performance of receiver when QR decomposition interference suppression combined with interference cancellation is used over independent Rayleigh fading channel. The different rate LDPC codes can be made by puncturing some rows of a given parity check matrix. This allows to implement a single encoder and decoder for different rate LDPC codes. The performance can be improved by assigning stronger LDPC codes in lower layer than upper layer because the poor SNR of first detected data streams makes error propagation. Keeping the same overall code rates, the V-BLAST system with different rate LDPC codes has the better performance (in terms of Bit Error Rate) than with constant rate LDPC code in fast fading channel.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2006년도 학술대회
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• pp.229-232
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• 2006

본 논문은 AWGN 채널상의 Single Parity Check(SPC) 다차원 product부호에서 LDPC(Low Density Parity Check)부호를 이용한 오류 정정의 성능을 제시한다. 기존 방법인 터보 부호 방식을 이용한 오류 정정과 비교하여 LDPC부호가 갖는 장점을 기술하고 실험을 통해 LDPC 부호를 이용한 오류 정정 성능도 터보부호와 대등함을 보인다.

• 한국통신학회논문지
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• 제31권11C호
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• pp.1030-1036
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• 2006

In this paper, we present two methods of correcting bit errors in constant amplitude multi-code (CAMC) CDMA, which uses the redundant bits only. The first method is a parity-based bit correction with hard-decision, where the received signals despread into n two-dimensional structure with both horizontal parity and vertical parity. Then, an erroneous bit is corrected for each $4{\times}4$ pattern. The second method is a turbo decoding, which is modified from the decoding of a single parity check product code (SPCPC). Experimental results show that, in the second method, the redundant bits in CAMC can be fully used for the error correction and so they are not really a loss of channel bandwidth. Hence, CAMC provides both a low peak-to-average power ratio and robustness to bit errors.