• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.389-396
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• 2008

The effect of thermal cycling on bond strength and residual stress at the interface between benzocyclobutene (BCB) and plasma enhanced chemical vapor deposited (PECVD) silicon dioxide ($SiO_2$) coated silicon wafers were evaluated by four point bending and wafer curvature techniques. Wafers were bonded using a pre-established baseline process. Thermal cycling was done between room temperature and a maximum peak temperature. In thermal cycling performed with 350 and $400^{\circ}C$ peak temperature, the bond strength increased substantially during the first thermal cycle. The increase in bond strength is attributed to the relaxation in residual stress by the condensation reaction of the PECVD $SiO_2$: this relaxation leads to increases in deformation energy due to residual stress and bond strength.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.441-448
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• 2015

Silicon carbide (SiC) coatings for tri-isotropic (TRISO) nuclear fuel particles were fabricated using a chemical vapor deposition (CVD) process onto graphite. A micro-tensile-testing system was developed for the mechanical characterization of SiC coatings at high temperatures. The fracture strength of the SiC coatings was characterized by the developed micro-tensile test in the range of $25^{\circ}C$ to $1000^{\circ}C$. Two types of CVD-SiC films were prepared for the micro-tensile test. SiC-A exhibited a large grain size (0.4 ~ 0.6 m) and the [111] preferred orientation, while SiC-B had a small grain size (0.2 ~ 0.3 mm) and the [220] preferred orientation. Free silicon (Si) was co-deposited onto SiC-B, and stacking faults also existed in the SiC-B structure. The fracture strengths of the CVD-SiC coatings, as measured by the high-temperature micro-tensile test, decreased with the testing temperature. The high-temperature fracture strengths of CVD-SiC coatings were related to the microstructure and defects of the CVD-SiC coatings.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.110-114
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• 2007

Dependence of the thermal stability of nickel silicide on the film stress of inter layer dielectric (ILD) layer has been investigated in this study and silicon nitride $(Si_3N_4)$ layer is used as an ILD layer. Nickel silicide was formed with a one-step rapid thermal process at $500^{\circ}C$ for 30 sec. $2000{\AA}$ thick $Si_3N_4$ layer was deposited using plasma enhanced chemical vapor deposition after the formation of Ni silicide and its stress was split from compressive stress to tensile stress by controlling the power of power sources. Stress level of each stress type was also split for thorough analysis. It is found that the thermal stability of nickel silicide strongly depends on the stress type as well as the stress level induced by the $Si_3N_4$ layer. In the case of high compressive stress, silicide agglomeration and its phase transformation from the low-resistivity nickel mono-silicide to the high-resistivity nickel di-silicide are retarded, and hence the thermal stability is obviously improved a lot. However, in the case of high tensile stress, the thermal stability shows the worst case among the stressed cases.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.79-79
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• 1999

The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.470.2-470.2
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• 2014

RF-PECVD 장치에 의해 증착된 실리콘 질화막(SiNx)은 결정질 실리콘 태양전지에서 반사 방지막 효과 및 우수한 표면 패시베이션 특성을 제공하는 것으로 알려져 있다. 본 논문에서는 실리콘 질화막의 패시베이션 특성을 향상시키기 위해서 공정온도를 $400^{\circ}C$로 고정하고 공정압력, 가스비, RF (radio frequency) power를 가변하였다. 이 때의 실리콘 질화막의 굴절률 및 두께는 각각 2.0, 80 nm로 증착하여 그에 따른 특성에 대해 분석하였다. 공정 압력이 감소할수록 실리콘 질화막이 증착된 결정질 실리콘 태양전지의 유효 반송자 수명이 증가함을 보였고, 반면에 증착속도는 감소하였다. 또한 RF-power 500 W에서 실리콘 질화막이 증착된 결정질 실리콘 태양전지의 유효 반송자 수명이 상대적으로 높았으며 출력이 올라갈수록 증착속도가 증가하였다. 결과적으로 결정질 실리콘 태양전지에 증착한 실리콘 질화막은 0.8torr 공정 압력과 RF-power 500 W에서 $38.8{\mu}s$로 가장 좋은 유효 반송자 수명을 확인하였다. 위의 결과를 바탕으로 결정질 실리콘 태양전지를 제작하였고 향상된 패시베이션 특성을 갖는 실리콘 질화막의 조건을 찾기 위해서 개방전압(open circuit voltage)을 비교하였다. 공정압력 0.8 torr, RF-power 500 W에서 가장 높은 결과를 보였으며 이는 유효 반송자 수명과 유사한 결과를 나타냈다. 하지만 낮은 FF (fill factor)로 인해 변환 효율이 낮은 결과를 보였다. 태양전지 제작시 낮은 fill factor를 보인 이유와 위의 단점을 보완하기 위해 추가 실험을 수행하였으며, 개선된 fill factor를 통해 18.3% 효율의 태양전지를 제작하였다.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1555-1558
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• 2002

This paper presents deposition and characterizations of microcrystalline silicon(${\mu}c$-Si:H) films prepared by hot wire chemical vapor deposition at substrate temperature below $300^{\circ}C$. The $SiH_4$ Concentration$[F(SiH_4)/F(SiH_4)+F(H_2)]$ is critical parameter for the formation of Si films with microcrystalline phase. At 6% of silane concentration, deposited intrinsic ${\mu}c$-Si:H films shows sufficiently low dark conductivity and high photo sensitivity for solar cell applications. P-type ${\mu}c$-S:H films deposited by Hot-Wire CVD also shows good electrical properties by varying the rate of $B_2H_6$ to $SiH_4$ gas. The solar cells with structure of Al/nip ${\mu}c$-Si:H/TCO/glass was fabricated with sing1e chamber Hot-Wire CVD. About 3% solar efficiency was obtained and applicability of HWCVD for thin film solar cells was proven in this research.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.312-312
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• 2011

In SiH4/H2 discharge for growth process of hydrogenated amorphous silicon (a-Si:H), silane polymers, produced by SiH2 + Sin-1H2n ${\rightarrow}$ SinH2n+2, have no reactivity on the film-growing surface. However, under the SiH2 rich condition, high silane reactive species (HSRS) can be produced by electron collision to silane polymers. HSRS, having relatively strong reactivity on the surface, can react with dangling bond and form Si-H2 networks which have a close correlation with photo-induced degradation of a-Si:H thin film solar cell [1]. To find contributions of suggested several external plasma conditions (pressure, frequency and ratio of mixture gas) [2,3] to suppressing productions of HSRS, some plasma characteristics are studied by numerical methods. For this study, a zero-dimensional global model for SiH4/H2 discharge and a one-dimensional particle-in-cell Monte-Carlo-collision model (PIC-MCC) for pure SiH4 discharge have been developed. Densities of important reactive species of SiH4/H2 discharge are observed by means of the global model, dealing 30 species and 136 reactions, and electron energy probability functions (EEPFs) of pure SiH4 discharge are obtained from the PIC-MCC model, containing 5 charged species and 15 reactions. Using global model, SiH2/SiH3 values were calculated when pressure and driving frequency vary from 0.1 Torr to 10 Torr, from 13.56 MHz to 60 MHz respectively and when the portion of hydrogen changes. Due to the limitation of global model, frequency effects can be explained by PIC-MCC model. Through PIC-MCC model for pure SiH4, EEPFs are obtained in the specific range responsible for forming SiH2 and SiH3: from 8.75 eV to 9.47 eV [4]. Through densities of reactive species and EEPFs, polymerization reactions and production of HSRS are discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.71-71
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• 2012

As the critical dimensions of integrated circuits are scaled down, the line width and spacing between the metal interconnects are made smaller. The dielectric film used as insulation between the metal lines contributes to the resistance-capacitance (RC) time constant that governs the device speed. If the RC time delay, cross talk and lowering the power dissipation are to be reduced, the intermetal dielectric (IMD) films should have a low dielectric constant. The introduction of Cu and low-k dielectrics has incrementally improved the situation as compared to the conventional $Al/SiO_2$ technology by reducing both the resistivity and the capacitance between interconnects. Some of the potential candidate materials to be used as an ILD are organic and inorganic precursors such as hydrogensilsequioxane (HSQ), silsesquioxane (SSQ), methylsilsisequioxane (MSQ) and carbon doped silicon oxide (SiOCH), It has been shown that organic functional groups can dramatically decrease dielectric constant by increasing the free volume of films. Recently, various inorganic precursors have been used to prepare the SiOCH films. The k value of the material depends on the number of $CH_3$ groups built into the structure since they lower both polarity and density of the material by steric hindrance, which the replacement of Si-O bonds with Si-$CH_3$ (methyl group) bonds causes bulk porosity due to the formation of nano-sized voids within the silicon oxide matrix. In this talk, we will be introduce some properties of SiOC(-H) thin films deposited with the dimethyldimethoxysilane (DMDMS: $C_4H_{12}O_2Si$) and oxygen as precursors by using plasma-enhanced chemical vapor deposition with and without ultraviolet (UV) irradiation.

• Current Photovoltaic Research
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• v.3 no.3
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• pp.80-84
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• 2015

We suggest new emitter formation method using solid-phase epitaxy (SPE); solid-phase epitaxy emitter (SEE). This method expect simplification and cost reduction of process compared with furnace process (POCl3 or BBr3). The solid-phase epitaxy emitter (SEE) deposited a-Si:H layer by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD) on substrate (c-Si), then thin layer growth solid-phase epitaxy (SPE) using rapid thermal process (RTP). This is possible in various emitter profile formation through dopant gas ($PH_3$) control at deposited a-Si:H layer. We fabricated solar cell to apply solid-phase epitaxy emitter (SEE). Its performance have an effect on crystallinity of phase transition layer (a-Si to c-Si). We confirmed crystallinity of this with a-Si:H layer thickness and annealing temperature by using raman spectroscopy, spectroscopic ellipsometry and transmission electron microscope. The crystallinity is excellent as the thickness of a-Si layer is thin (~50 nm) and annealing temperature is high (<$900^{\circ}C$). We fabricated a 16.7% solid-phase epitaxy emitter (SEE) cell. We anticipate its performance improvement applying thin tunnel oxide (<2nm).