• 제목/요약/키워드: Silicon vapor

검색결과 670건 처리시간 0.03초

실리콘이 첨가된 다이아몬드상 카본 필름의 트라이볼로지적 특성에 미치는 환경변화의 영향 (Effect of environment on the tribological behavior of Si-incorporated diamond-like carbon films)

  • 양승호;공호성;이광렬;박세준;김대은
    • 한국윤활학회:학술대회논문집
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    • 한국윤활학회 1999년도 제30회 추계학술대회
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    • pp.42-48
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    • 1999
  • An experimental study was performed to discover the effect of environment on the tribological behavior of Si-incorporated diamond-like carbon(Si-DLC) film slid on a steel ball. The films were deposited on Si(100) wafers from radio-frequency glow discharge of mixtures of benzene and dilute silane gases. Experiments using a ball-on-disk test-rig was performed under vacuum, dry air and ambient air conditions. It was observed that coefficient of friction was decreased as the environmental condition changes from vacuum, to dry air. It was also observed that the coefficient of friction decreased with increasing silicon concentration in the film. Chemical analyses of debris suggested that the low and stable friction coefficient is closely related to the silicon rich oxide debris and the rolling action.

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RF-PECVD법에 의한 Ti-Si-N 박막의 증착거동 (Deposition Behaviors of Ti-Si-N Thin Films by RF Plasma-Enhanced Chemical Vapor Deposition.)

  • 이응안;이윤복;김광호
    • 한국표면공학회지
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    • 제35권4호
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    • pp.211-217
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    • 2002
  • Ti-Si-N films were deposited onto WC-Co substrate by a RF-PECVD technique. The deposition behaviors of Ti-Si-N films were investigated by varying the deposition temperature, RF power, and reaction gas ratio (Mx). Ti-Si-N films deposited at 500, 180W, and Mx 60% had a maximum hardness value of 38GPa. The microstructure of films with a maximum hardness was revealed to be a nanocomposite of TiN crystallites penetrated by amorphous silicon nitride phase by HRTEM analyses. The microstructure of maximum hardness with Si content (10 at.%) was revealed to be a nanocomposite of TiN crystallites penetrated by amorphous silicon nitride phase, but to have partly aligned structure of TiN and some inhomogeniety in distribution. and At above 10 at.% Si content, TiN crystallite became finer and more isotropic also thickness of amorphous silicon nitride phase increased at microstructure.

Silicon Carbide Coating on Graphite and Isotropic C/C Composite by Chemical Vapour Reaction

  • Manocha, L.M.;Patel, Bharat;Manocha, S.
    • Carbon letters
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    • 제8권2호
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    • pp.91-94
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    • 2007
  • The application of Carbon and graphite based materials in unprotected environment is limited to a temperature of $450^{\circ}C$ or so because of their susceptibility to oxidation at this temperature and higher. To over come these obstacles a low cost chemical vapour reaction process (CVR) was developed to give crystalline and high purity SiC coating on graphite and isotropic C/C composite. CVR is most effective carbothermal reduction method for conversation of a few micron of carbon layer to SiC. In the CVR method, a sic conversation layer is formed by reaction between carbon and gaseous reagent silicon monoxide at high temperature. Characterization of SiC coating was carried out using SEM. The other properties studied were hardness density and conversion efficiency.

Silicon Nitride Films Prepared at a Low Temperature (${\leq}200^{\circ}C$) for Gate Dielectric of Flexible Display

  • Lee, Kyoung-Min;Hwang, Jae-Dam;Lee, Youn-Jin;Hong, Wan-Shick
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1402-1404
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    • 2009
  • The silicon nitride films for gate dielectric were deposited by catalytic chemical vapor deposition at low temperature (${\leq}200^{\circ}C$). The mixture of $SiH_4$, $NH_3$ and $H_2$ was used as source gases. The current-voltage (I-V) and the capacitance-voltage (C-V) characteristics of the films were measured. The breakdown voltage and the flat band voltage shift of samples were improved by increase of the $NH_3$ contents and $H_2$ dilution ratio. The defect states were analyzed by photoluminescence (PL) spectra. As the defect states decreased, the breakdown voltage and the flat band voltage shift increased.

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Residual stress on nanocrystalline silicon thin films deposited with substrate biasing at low temperature

  • Lee, Hyoung-Cheol;Kim, In-Kyo;Yeom, Geun-Young
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1568-1570
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    • 2009
  • Nanocrystalline silicon thin films were deposited using an internal-type inductively coupled plasma-chemical vapor deposition at room temperature by varying the bias power to the substrate and the structural characteristics of the deposited thin film were investigated. The result showed that the crystalline volume fraction was decreased with the increase of bias power. At the low bias power range of 0~60 W, the compress stress in the deposited thin film was in the range of -34 ~ -77 Mpa which is generally lower than the residual stress observed for the nanocrystalline silicon thin films deposited by capacitively coupled plasma.

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SOI 응용을 위한 반도체-원자 초격자 구조의 특성 (Characteristics of Semiconductor-Atomic Superlattice for SOI Applications)

  • 서용진
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제53권6호
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    • pp.312-315
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    • 2004
  • The monolayer of oxygen atoms sandwiched between the adjacent nanocrystalline silicon layers was formed by ultra high vacuum-chemical vapor deposition (UHV-CVD). This multilayer Si-O structure forms a new type of superlattice, semiconductor-atomic superlattice (SAS). According to the experimental results, high-resolution cross-sectional transmission electron microscopy (HRTEM) shows epitaxial system. Also, the current-voltage (Ⅰ-Ⅴ) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the system may form an epitaxially grown insulating layer as possible replacement of silicon-on-insulator (SOI), a scheme investigated as future generation of high efficient and high density CMOS on SOI.

두 단계 열처리에 의해 제작된 다결정 실리콘 박막트랜지스터의 전기적 특성의 분석 (Analysis of electrical properties of two-step annealed polycrystalline silicon thin film transistors)

  • 최권영;한민구;김용상
    • 대한전기학회논문지
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    • 제45권4호
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    • pp.568-573
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    • 1996
  • The amorphous silicon films deposited by low pressure chemical vapor deposition are crystallized by the various annealing techniques including low-temperature furnace annealing and two-step annealing. Two-step annealing is the combination of furnace annealing at 600 [.deg. C] for 24 h and the sequential furnace annealing at 950 [.deg. C] 1h or the excimer laser annealing. It s found that two-step annealings reduce the in-grain defects significantly without changing the grain boundary structure. The performance of the poly-Si thin film transistors (TFTs) produced by employing the tow-step annealing has been improved significantly compared with those of one-step annealing. (author). 13 refs., 6 figs., 1 tab.

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입자 핵연료의 SiC/C 다층 도포층의 미세조직 및 극미세 경도 평가 (Microstructure and Nano-hardness of SiC/C Multi-coated Layers on a Particulate Nuclear Fuel)

  • 최용
    • 한국표면공학회지
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    • 제52권6호
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    • pp.321-325
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    • 2019
  • Triso-type coating layers of silicon carbide and graphite on UO2 paticulate nuclear fuel were prepared by using fluidized bed type chemical vapor deposition and self-propagating high temperature synthesis methods to make a coated nuclear fuel of a power plant for hydrogen mass-production. The source and carrier gases were the mixture of methyltrichlorosilane and propane, and inert argon. Chemical analysis and microstructure observation showed that the coated layers were inner graphite, middle silicon carbide and outer graphite. The elastic modulus and nano-hardness of the silicon carbide layer were 503 [GPa] and 36 [GPa], respectively.

비정질 실리콘 박막에서 결정상 실리콘의 입자성장에 관한 고분해능 투과전자현미경에 의한 연구 (A High-Resolution Transmission Electron Microscopy Study of the Grain Growth of the Crystalline Silicon in Amorphous Silicon Thin Films)

  • 김진혁;이정용;남기수
    • 전자공학회논문지A
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    • 제31A권7호
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    • pp.85-94
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    • 1994
  • A high-resolution transmission electron microscopy study of the solid phase crystallization of the amorphous silicon thin films, deposited on SiOS12T at 52$0^{\circ}C$ by low pressure chemical vapor deposition and annealed at 55$0^{\circ}C$ in a dry N$_{2}$ ambient was carried out so that the arrangement of atoms in the crystalline silicon and at the amorphous/crystalline interface of the growing grains could be understood on an atomic level. Results show that circular crystalline silicon nuclei have formed and then the grains grow to an elliptical or dendritic shape. In the interior of all the grains many twins whose{111} coherent boundaries are parallel to the long axes of the grains are observed. From this result, it is concluded that the twins enhance the preferential grain growth in the <112> direction along {111} twin planes. In addition to the twins. many defect such as intrinsic stacking faults, extrinsic stacking faults, and Shockley partial dislocations, which can be formed by the errors in the stacking sequence or by the dissociation of the perfect dislocation are found in the silicon grain. But neither frank partial dislocations which can be formed by the condensation of excess silicon atoms or vacancies and can form stacking fault nor perfect dislocations which can be formed by the plastic deformation are observed. So it is concluded that most defects in the silicon grain are formed by the errors in the stacking sequence during the crystallization process of the amorphous silicon thin films.

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결정질 실리콘 태양전지의 이중 반사방지막 특성에 대한 연구 (Characteristics of Crystalline Silicon Solar Cells with Double Layer Antireflection Coating by PECVD)

  • 김진국;박제준;홍지화;김남수;강기환;유권종;송희은
    • 한국태양에너지학회:학술대회논문집
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    • 한국태양에너지학회 2012년도 춘계학술발표대회 논문집
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    • pp.243-247
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    • 2012
  • The paper focuses on an anti-reflection (AR) coating deposited by PECVD in silicon solar cell fabrication. AR coating is effective to reduce the reflection of the light on the silicon wafer surface and then increase substantially the solar cell conversion efficiency. In this work, we carried out experiments to optimize double AR coating layer with silicon nitride and silicon oxide for the silicon solar cells. The p-type mono crystalline silicon wafers with $156{\times}156mm^2$ area, 0.5-3 ${\Omega}{\cdot}cm$ resistivity, and $200{\mu}m$ thickness were used. All wafers were textured in KOH solution, doped with $POCl_3$ and removed PSG before ARC process. The optimized thickness of each ARC layer was calculated by theoretical equation. For the double layer of AR coating, silicon nitride layer was deposited first using $SiH_4$ and $NH_3$, and then silicon oxide using $SiH_4$ and $N_2O$. As a result, reflectance of $SiO_2/SiN_x$ layer was lower than single $SiN_x$ and then it resulted in increase of short-circuit current and conversion efficiency. It indicates that the double AR coating layer is necessary to obtain the high efficiency solar cell with PECVD already used in commercial line.

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