• 대한금속재료학회지
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• 제50권8호
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• pp.575-582
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• 2012

Medium carbon steel was aluminized by hot dipping into molten Al or Al-1 at% Si baths. After hot-dipping in these baths, a thin Al-rich topcoat and a thick alloy layer rich in $Al_5Fe_2$ formed on the surface. A small amount of FeAl and $Al_3Fe$ was incorporated in the alloy layer. Silicon from the Al-1 at% Si bath was uniformly distributed throughout the entire coating. The hot dipping increased the microhardness of the steel by about 8 times. Heating at $700-1000^{\circ}C$, however, decreased the microhardness through interdiffusion between the coating and the substrate. The oxidation at $700-1000^{\circ}C$ in air formed a thin protective ${\alpha}-Al_2O_3$ layer, which provided good oxidation resistance. Silicon was oxidized to amorphous silica, exhibiting a glassy oxide surface.

• 한국전기전자재료학회논문지
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• 제37권3호
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• pp.337-344
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• 2024

This work focuses on improving the light-harvesting efficiency of thin-film silicon solar cells through innovative multi-architecture surface modifications. To create a regular optical structure, a lithographic process was performed to form it on a glass substrate through various etching processes, from Etch-1 to Etch-3. AZO was deposited on top of the structures and re-etched to create a multi-architectural surface. These surface-modified structures improved the light absorption and overall performance of the solar cell through changes in optical and physical properties, which we will analyze. In addition, we investigated the effect of post-cleaning on the etched glass structures through EDX analysis to understand the mechanism of the etching action. The results of this study are expected to provide important guidelines for the design and fabrication of solar cells and other photovoltaic devices.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• 대한전자공학회논문지
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• 제21권5호
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• pp.46-54
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• 1984

3μm 게이트 길이를 가지는 n-well CMOS 공정이 개발되었고 이의 응용 가능성을 검토하였다. Thres-hold 전압은 이온주입으로 쉽게 조절할 수 있으며, 3μm 채널 길이에서 short 채널 효과는 무시할 수 있다. Contact 저항에 있어서 Al-n+ 저항값이 커서 VLSI 소자의 제작에 장애 요인이 될 것으로 보인다. CMOS inverter의 transfer 특성은 양호하며, (W/L) /(W/L) =(10/5)/(5/5)인 89단의 ring oscillator로부터 구한 게이트당 전달 지연 시간은 3.4nsec 정도이다. 본 공정의 설계 규칙에서 n-well과 p-substrate에 수 mA의 전류가 흐를 때 latch-up이 일어나며, well 농도와 n+소오스-well간의 간격에 크게 영향을 받는다. 따라서 공정과 설계 규칙의 변화에 따른 latch-up 특성에 집중적인 연구가 필요할 것으로 사료된다.

• Korean Chemical Engineering Research
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• 제46권1호
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• pp.50-55
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• 2008

RF plasma CVD법을 이용하여 금속 촉매(Fe)가 증착된 $SiO_2$ 기판 위에 $H_2$와 $C_2H_2$의 혼합가스를 사용하여 증착된 탄소나노튜브(carbon nanotube, CNT)의 특성에 대한 기판의 온도의 영향을 조사하였다. $SiO_2$ 위에 철 촉매는 RF 마그네트론 스퍼터에 의해 만들어졌다. 고 순도의 나노튜브 박막을 얻기 위해서 기판 홀더 위에 접지된 그리드 메쉬 커버를 설치하였다. 증착된 CNT의 표면 미세구조 및 화학적 구조를 SEM, Raman, XPS, 그리고 TEM으로 측정하였다. 증착된 CNT 박막들은 대나무 같은 다중벽 구조를 가지는 탄소 파이버 형태였으며 $55^{\circ}C$에서 보다 $600^{\circ}C$에서 보다 더 치밀한 구조를 보이나 $650^{\circ}C$에서는 밀도가 다소 감소함을 알 수 있었다.

• 한국세라믹학회지
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• 제39권4호
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• pp.394-400
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• 2002

리튬 이차전지용 부극재료로 미량의 실리콘이 첨가된 주석산화물 박막을 R.F. magnetron sputtering법을 이용하여 제조하였다. 실리콘의 첨가로 인해 주석의 산화상태를 감소시켜서 첫 번째 충방전 동안 비가역성을 감소시키는 전기 화학적 결과를 얻을 수 있었다. 주석 산화물 박막의 결정 배향성은 기판온도가 올라감에 따라서 (110),(101),(211) 면들이 성장하였다. 합성된 박막은 기판온도가 $300^{\circ}C$이고 $Ar:O_2$의 비가 7:3일때, 700mAh/g의 에너지 밀도를 가지며 가장 좋은 가역성능을 보여주었다.

• 한국전기전자재료학회논문지
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• 제31권4호
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• pp.203-207
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• 2018

In this work, we investigate the effects of lithium doping on the electric performance of solution-processed n-type zinc tin oxide (ZTO)/p-type silicon carbide (SiC) heterojunction diode structures. The proper amount of lithium doping not only affects the carrier concentration and interface quality but also influences the temperature sensitivity of the series resistance and activation energy. We confirmed that the device characteristics vary with lithium doping at concentrations of 0, 10, and 20 wt%. In particular, the highest rectification ratio of $1.89{\times}107$ and the lowest trap density of $4.829{\times}1,022cm^{-2}$ were observed at 20 wt% of lithium doping. Devices at this doping level showed the best characteristics. As the temperature was increased, the series resistance value decreased. Additionally, the activation energy was observed to change with respect to the component acting on the trap. We have demonstrated that lithium doping is an effective way to obtain a higher performance ZTO-based diode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.63.1-63
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• 2003

Catalytic chemical vapor deposition (Cat-CVD) has been developed to deposit alumina(Al$_2$O$_3$) thin films on silicon (Si) crystal using N$_2$ bubbled tir-methyl aluminium [Al(CH$_3$)$_3$, TMA] and molecular oxygen (O$_2$) as source species and tungsten wires as a catalyzer. The catalyzer dissociated TMA at approximately 600$^{\circ}C$ The maximum deposition rate was 18 nm/min at a catalyzer temperature of 1000 and substrate temperature of 800$^{\circ}C$. Metal oxide semiconductor (MOS) diodes were fabricated using gates composed of 32.5-nm-thick alumina film deposited as a substrate temperature of 400oC. The capacitance measurements resulted in a relatively dielectric constant of 7, 4, fixed charge density of 1.74*10e12/$\textrm{cm}^2$, small hysteresis voltage of 0.12V, and very few interface trapping charge. The leakage current was 5.01*10e-7 A/$\textrm{cm}^2$ at a gate bias of 1V.

• 대한전자공학회논문지SD
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• 제41권4호
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• pp.9-14
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• 2004

매몰 산화층 밑의 실리콘 기판에 자기정렬 방법으로 ground plane 전극을 만든 SOI MOSFET의 단채널 현상과 Punchthrough 특성을 측정·분석하였다. 채널 길이가 $0.2{\mu}m$ 이하의 소자에서는 GP-SOI 소자가 FD-SOI 소자보다 채널 길이에 따른 문턱전압 저하 및 subthreshold swing이 작고 DIBL 현상이 크게 개선됨을 알 수 있었다. 기판전압에 따른 문턱전압 특성으로부터 GP-SOI 소자의 body factor가 FD-SOI 소자보다 큰 것을 알 수 있었다. 그리고 punchthrough 전압 특성으로부터 GP-SOI 소자의 punchthrough 전압이 FD-SOI 소자보다 큰 것을 알 수 있었다.