• Journal of the Korean Society for Heat Treatment
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• v.26 no.4
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• pp.178-184
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• 2013

The effects of thickness and surface grinding condition on the fracture strength of Si wafer with a thickness under $100{\mu}m$ were investigated. Fracture strength was measured by ball breaker test for about 330 dies (size: $4mm{\times}4mm$) per each wafer. For statistical analysis of the fracture strength, scale factor was determined from Weibull plot. Ball breaker fracture strength was observed to increase with decreasing thickness of silicon die. For the silicon dies of different surface conditions, ball breaker fracture strength was high in the order of polished, ground (#4800), and ground (#320 grit) specimen. Probabilistic fracture strength (i.e., scale factor) increased with decreasing surface roughness of silicon die.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.15-21
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• 2011

In this study, flexural strength and fracture behavior of silicon die from single crystalline silicon wafer were investigated as a function of thickness. Silicon wafers with various thickness of 300, 200, 180, 160, 150, and 100 ${\mu}m$ were prepared by mechanical grinding and polishing of as-saw wafers. Flexural strength of 40 silicon dies (size: 62.5 mm${\times}$4 mm) from each wafer was measured by four point bending test, respectively. For statistical analysis of flexural strength, shape factor(i.e., Weibull modulus) and scale factor were determined from Weibull plot. Flexural strength reflecting both statistical fracture probability and size (thickness) effect of brittle silicon die was obtained as a linear function of die thickness. Fracture appearance was discussed in relation with measured fracture strength.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.361-365
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• 2022

Advanced packaging demands are driven by the need for dense integration systems. Consequently, stacked packaging technology has been proposed instead of reducing the ultra-fine patterns to secure economic feasibility. This study proposed an effective packaging process technology for semiconductor devices using a 9-inch dicing die attach film (DDAF), wherein the die attach and dicing films were combined. The process involved three steps: tape lamination, dicing, and bonding. Following the grinding of a silicon wafer, the tape lamination process was conducted, and the DDAF was arranged. Subsequently, a silicon wafer attached to the DDAF was separated into dies employing a blade dicing process with a two-step cut. Thereafter, one separated die was bonded with the other die as a substrate at 130 ℃ for 2 s under a pressure of 2 kgf and the chip was hardened at 120 ℃ for 30 min under a pressure of 10 kPa to remove air bubbles within the DAF. Finally, a curing process was conducted at 175 ℃ for 2 h at atmospheric pressure. Upon completing the manufacturing processes, external inspections, cross-sectional analyses, and thermal stability evaluations were conducted to confirm the optimality of the proposed technology for application of the DDAF. In particular, the shear strength test was evaluated to obtain an average of 9,905 Pa from 17 samples. Consequently, a 3D integration packaging process using DDAF is expected to be utilized as an advanced packaging technology with high reliability.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.887-890
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• 2008

We present 2D slab silicon-based photonic crystal optical insulator to enhance light emission efficiency of light-emitting diode (LED). A 2D slab silicon photonic crystal is designed in such a way that light emitting diode die can be placed in the middle of the silicon photonic crystal. The device creates light propagation forbidden region in horizontal plane for Transverse Electric (TE) light with the wavelength range of 450 nm to 600 nm.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.327-329
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• 2006

In this paper, the cutting qualities by laser dicing and fracture strength of a silicon die is investigated. Laser micromachining is the non-contact process using thermal ablation and evaporation mechanisms. By these mechanisms, debris is generated and stick on the surface of wafer, which is the problem to apply laser dicing to semiconductor manufacture process. Unlike mechanical sawing using diamond blade, chipping on the surface and crack on the back side of wafer isn't made by laser dicing. Die strength by laser dicing is measured via the three-point bend test and is compared with the die strength by mechanical sawing. As a results, die strength by laser dicing shows a decrease of 50% in compared with die strength by mechanical sawing.

• Design & Manufacturing
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• v.7 no.1
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• pp.55-59
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• 2013

A Light Emitting Diode(LED) is a semiconductor device which converts electricity into light. LEDs are widely used in a field of illumination, LCD(Liquid Crystal Display) backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. In general, LEDs production does die bonding and wire bonding on board, and do silicon and phosphor dispensing to protect LED chip and improve brightness. Then lens molding process is performed using mixed liquid silicon rubber(LSR) by resin and hardener. A mixture of resin and hardener affect the optical characteristics of the LED lens. In this paper, computational design of static mixer was performed for mixing of liquid silicon. To evaluate characteristic of mixing efficiency, finite element model of static mixer was generated, and fluidic analysis was performed according to length of mixing element. Finally, optimal condition of length of mixing element was applied to static mixer from result of fluidic analysis.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.6
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• pp.37-43
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• 1997

The technology of Laser lamination joining of silicon steel sheets has been studied in this paper. Conventional sheets lamination process does not meet the requirments for the improvement electric parts performance. In response to this, a new Laser spot joining method has been developed. This study performs the Laser spot lamination joining while synchronizing the sillicon steel sheets in the dies with the press movement. Several conclusions have been drawn in this paper. Effects of beam focus, power, atmosphere gas and press oil etc.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.467-468
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• 2007