• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.6
• /
• pp.367-371
• /
• 2018

1,200 V class junction barrier schottky (JBS) diodes and schottky barrier diodes (SBD) were simultaneously fabricated on the same 4H-SiC wafer. The resulting diodes were characterized at temperatures from room temperature to 473 K and subsequently compared in terms of their respective I-V characteristics. The parameters deduced from the observed I-V measurements, including ideality factor and series resistance, indicate that, as the temperature increases, the threshold voltage decreases whereas the ideality factor and barrier height increase. As JBS diodes have both Schottky and PN junction structures, the proper depletion layer thickness, $R_{on}$, and electron mobility values must be determined in order to produce diodes with an effective barrier height. The comparison results showed that the JBS diodes exhibit a larger effective barrier height compared to the SBDs.

• Proceedings of the Korean Institute of Resources Recycling Conference
• /
• 2006.05a
• /
• pp.47-55
• /
• 2006

Recovery of acids from the waste etching solution of containing nitric, hydrofluoric and acetic acid discharged from silicon wafer manufacturing process has been attempted by using solvent extraction method. With EHA (2-Ethylhexlalcohol) for acetic acid and TBP(Tri-butly Phosphate) for nitic and hydrofluoric acid as extraction agent was carried on experiment to obtain the process design data in separation procedure. From the McCabe-Thiele diagram analysis, we obtained the optimum conditions of phase ratio(O/A) and stages to separate the each acid sequently from the mixture acids. The recovery yield was obtained 90% above for acetic acid from the acid mixtures, 90% above for nitric acid from acetic acid extraction raffinate and then 67% above for hydrofluoric acid from final extraction raffinate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.111-111
• /
• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.1295-1297
• /
• 1993

Properties of oxynitride films oxidized by $N_2O$ gas after thermal oxidation and $N_2O$ oxide films directly oxidized using $N_2O$ gas on the bare silicon wafer have been studied. Through the AES analysis, Nitrogen pile-up at the interface of Si/oxynitride and Si/$N_2O$ oxide has observed. Also, it could be presumed that there are differences in the mechanism of the growth of film by observing film growth. $N_2O$ oxide and oxynitride films have the self-limited characteristics. Therefore, it will be possible to obtain ultra-thin films. Nitrogen pile-up at the interfaces Si/oxynitride and Si/$N_2O$ oxide strengthens film structure and improves dielectric reliability. Although fixed charge densities and interface trap densities of $N_2O$ oxide and oxynitride films has somewhat higher than those of thermal $SiO_2,\;N_2O$ oxide and oxynitride films showed improved I-V characteristics and constant current stress.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.1268-1270
• /
• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.169-170
• /
• 2006

In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2000.02a
• /
• pp.80-80
• /
• 2000

Surface acoustic wave (SAW) devices have become more important as mobile telecommunication systems need h호-frrequency, low-loss, and down-sized components. Higher-frequency SAW divices can be more sasily realized by developing new h호-SAW-velocity materials. The ZnO/diamond/Si multilasyer structure is one of the most promising material components for GHz-band SAW filters because of its SAW velocity above 10,000 m/sec. Silicon carbide is also a potential candidate material for high frequency, high power and radiation resistive electronic devices due to its superior mechanical, thermal and electronic properties. However, high price of commercialized 6- or 4H-SiC single crystalline wafer is an obstacle to apply SiC to high frequency SAW devices. In this study, single crystalline 3C-SiC thin films were grown on Si (100) by MOCVD using bis-trimethylsilymethane (BTMSM, C7H20Si7) organosilicon precursor. The 3C-SiC film properties were investigated using SEM, TEM, and high resolution XRD. The FWHM of 3C-SiC (200) peak was obtained 0.37 degree. To investigate the SAW propagation characteristics of the 3C-SiC films, SAW filters were fabricated using interdigital transducer electrodes on the top of ZnO/3C-SiC/Si(100), which were used to excite surface acoustic waves. SAW velocities were calculated from the frequency-response measurements of SAW filters. A generalized SAW mode. The hard 3C-SiC thin films stiffened Si substrate so that the velocities of fundamental and the 1st mode increased up to 5,100 m/s and 9,140 m/s, respectively.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.31-32
• /
• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Korean Journal of Metals and Materials
• /
• v.48 no.7
• /
• pp.667-673
• /
• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
• /
• v.50 no.2
• /
• pp.152-158
• /
• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.