• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1999년도 PROCEEDINGS OF KACG FALL MEETING, SEOUL, 4 DECEMBER, 1999
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• pp.100-111
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• 1999

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.54-54
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• 2009

Ag thick film has been used for electrode materials with the excellent conductivity. Ag electrode is used in screen-printed silicon solar cells as a electrode material. Compared to photolithography and buried-contact technology, screen-printing technology has the merit of fabricating low-priced cells and enormous cells in a few hours. Ag paste consists of Ag powders, vehicles and additives such as frits, metal powders (Pb, Bi, Zn). Frits accelerate the sintering of Ag powders and induce the connection between Ag electrode and Si wafer. Thermophysical properties of frits and reactions among Ag, frits and Si influence on cell performance. In this study, Ag pastes were fabricated with adding different kinds of frits. After Ag pastes were printed on silicon wafer by screen-printing technology, the cells were fired using a belt furnace. The cell parameters were measured by light I-V to determine the short-circuit current, open-circuit voltage, FF and cell efficiency. In order to study the relationship between the reactivity of Ag, frit, Si and the electrical properties of cells, the reaction of frits and Si wafer on was studied with thermal properties of frits. The interface structure between Ag electrode and Si wafer were also measured for understanding the reactivity of Ag, frit and Si wafer. The excessive reactivity of Ag, frit and Si wafer certainly degraded the electrical properties of cells. These preliminary studies suggest that reactions among Ag, frits and Si wafer should optimally be controlled for cell performances.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.346.2-346.2
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• 2016

The rear side contact recombination in the crystalline silicon solar cell could be reduced by back surface field. We formed polycrystalline silicon as a back surface field through crystallization of amorphous silicon. A thin silicon oxide applied to the passivation layer. We used quasi-steady-state photoconductance measurement to analyze electrical properties with various annealing condition. And, blister formed on surface of wafer during the annealing process. We observed the blister after varied annealing process with wafer of various surface. Shape and density of blister is influenced by various annealing temperature and process time. As the annealing temperature became higher, the average diameter of blister is decreased and total number of blister is increased. The sample with the $600^{\circ}C$ annealing temperature and 1 min annealing time exhibited the highest implied open circuit voltage and lifetime. We predicted that the various shape and density of blister affects the lifetime and implied open circuit voltage.

• Transactions on Electrical and Electronic Materials
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• 제4권3호
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• pp.29-33
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• 2003

Tri-crystalline silicon wafers have three different orientations and three-grain boundaries. In this paper, tri-crystalline silicon (tri-Si) wafers have been used for the fabrication of buried contact solar cells. The optical and micro-structural properties of these cells after texturing in KOH solution have been investigated and compared with those of cast mult- crystalline silicon (multi-Si) wafers. We employed a cost effective fabrication process and achieved buried contact solar cell (BCSC) energy conversion efficiencies up to $15\%$ whereas the cast multi-Si wafer has efficiency around $14\%$.

• 통합자연과학논문집
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• 제7권4호
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• pp.221-226
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• 2014

Optically encoded porous silicon smart particles were successfully fabricated from the free-standing porous silicon thin films using ultrasono-method. DBR PSi was prepared by an electrochemical etch of heavily doped $p^{{+}{+}}$-type silicon wafer. DBR PSi was prepared by using a periodic pseudo-square wave current. The surface-modified DBR PSi was prepared by either thermal oxidation or thermal hydrosilylation. Free-standing DBR PSi films were generated by lift-off from the silicon wafer substrate using an electropolishing current. Free-standing DBR PSi films were ultrasonicated to create DBR-structured porous smart particles. Optical characteristics of porous smart particles were measured by FT-IR spectroscopy. The surface morphology of porous smart particles was determined by FE-SEM.

• 한국결정성장학회지
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• 제26권5호
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• pp.171-174
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• 2016

The diamond wire sawing method to produce silicon wafers for the photovoltaic application is still a new and highly investigated wafering technology. This technology, featured as the higher productivity, lower wear of the wire, and easier recycling of the coolant, is expected to become the mainstream technique for slicing the silicon crystals. However, the saw marks on the wafer surface have to be investigated and improved. This paper discusses the removal of saw marks on diamond wire-sawn single crystalline silicon wafer. With a pretreatment step using tetramethyl ammonium hydroxide ($(CH_3)_4NOH$, TMAH) and conventional texturing process with KOH solution (1 % KOH, 8 % IPA, and DI water), the saw marks on the surface of the diamond wire-sawn silicon wafers can be effectively removed and they are invisible to naked eyes completely.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권6호
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• pp.271-277
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• 2002

In this paper, a MEMS silicon package is newly designed, fabricated for HMIC, and characterized for microwave and millimeter-wave device applications. The proposed package is fabricated by using two high resistivity silicon substrates and surface/bulk micromachining technology. It has a good performance characteristic such as -20㏈ of $S_11$/ and -0.3㏈ of $S_21$ up to 20㎓, which is useful in microwave region. It has also better heat transfer characteristics than the commonly used ceramic package. Since the proposed silicon MEMS package is easy to fabricate and wafer level chip scale packaging is also possible, the production cost can be much lower than the ceramic package. Since it will be a promising low-cost package for mobile/wireless applications.

• 한국태양에너지학회 논문집
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• 제32권spc3호
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• pp.194-198
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• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 80% of the market, despite the development of various thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon materials remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner the silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials with different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With less amount of paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 120 micron thickness of the wafer even though the conversion efficiency decrease by 0.5% occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al layer application.

• 대한화학회지
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• 제43권4호
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• pp.412-417
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• 1999

실리콘 웨이퍼 중의 금속 불순물을 유도결합플라스마-질량분석기(ICP-MS)로 분석하기 위한 시료의 전처리 방법으로 마이크로파 분해법과 산분해법을 비교하였다 $HNO_3$-HF 혼합용액을 실리콘 웨이퍼 시료에 가하고 마이크로파 분해법과 산분해법으로 용해시킨 후, 용액의 실리콘 매트릭스는 증발 용기 안에서 Si-F의 형태로 증발시켜 분석하였다. 실제 시료에 spike한 Ni, Cr 및 Fe의 회수율은 두 전처리 방법에서 95∼106%였다. Cu의 경우는 산분해법이 회수율이 더 좋았고, Zn의 경우는 마이크로파 분해법으로 전처리 한 경우의 회수율이 더 좋았다. Spin coater로 Fe를 오염시킨 실리콘 웨이퍼를 산분해법과 마이크로파 분해법으로 전처리하여 ICP-MS로 분석한 결과, Fe의 농도는 위의 두 전처리 방법에서 거의 차이가 없었다.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.374-377
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• 2002

Magnetic field is necessary to control the convection of melted silicon and to improve the quality of the wafer in the 12inch silicon wafer growing process. Nowadays, superconducting magnet is used in this process. We fabricated and tested a saddle shaped superconducting magnet for 8inch silicon wafer growing system. And the protection circuits for HTS current lead and superconducting coil are designed and manufactured. In this paper, their manufacturing process and test results are introduced.