• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.63-67
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• 2008

3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to $30{\mu}m\;or\;50{\mu}m$ thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.128-128
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• 2010

In this study, we investigated the evolution and reduction of the surface roughness during the high-speed chemical dry thinning process of Si wafers. The direct injection of NO gas into the reactor during the supply of F radicals from NF3 remote plasmas was very effective in increasing the Si thinning rate, due to the NO-induced enhancement of the surface reaction, but resulted in the significant roughening of the thinned Si surface. However, the direct addition of Ar and N2 gas, together with NO gas, decreased the root mean square (RMS) surface roughness of the thinned Si wafer significantly. The process regime for the increasing of the thinning rate and concomitant reduction of the surface roughness was extended at higher Ar gas flow rates. In this way, Si wafer thinning rate as high as $20\;{\mu}m/min$ and very smooth surface roughness was obtained and the mechanical damage of silicon wafer was effectively removed. We also measured die fracture strength of thinned Si wafer in order to understand the effect of chemical dry thinning on removal of mechanical damage generated during mechanical grinding. The die fracture strength of the thinned Si wafers was measured using 3-point bending test and compared. The results indicated that chemical dry thinning with reduced surface roughness and removal of mechanical damage increased the die fracture strength of the thinned Si wafer.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.392-392
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• 2010

In this study, high-speed chemical dry thinning process of Si wafer and evolution of surface roughness were investigated. Direct injection of NO gas into the reactor during the supply of F radicals from $NF_3$ remote plasmas was very effective in increasing the Si thinning rate due to the NO-induced enhancement of surface reaction but thinned Si surface became roughened significantly. Addition of Ar gas, together with NO gas, decreased root mean square (RMS) surface roughness of thinned Si wafer significantly. The process regime for the thinning rate enhancement with reduced surface roughness was extended at higher Ar gas flow rate. Si wafer thinning rate as high as $22.8\;{\mu}m/min$ and root-mean-squared (RMS) surface roughness as small as 0.75 nm could be obtained. It is expected that high-speed chemical dry thinning process has possibility of application to ultra-thin Si wafer thinning with no mechanical damage.

• Journal of the Korean Ceramic Society
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• v.45 no.2
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• pp.99-104
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• 2008

Zeta potential, sedimentation bulk density and rheology in the dispersion system have been studied in terms of solid loading (40-55 vol%), and types of additives. Ammonium polymethacrylate, glycerol, ethoxylated acetylenic diol, and polyvinyl alcohol have been used as the dispersant, cryo-protectant, surfactant, and binder, respectively. Sedimentation density greatly increased upon adding dispersant; the effect was more pronounced with ionic alumina suspension compared with covalent silicon carbide. With further addition of cryo-protectant and surfactant to dispersant, the sedimentation density increased somewhat. The suspension viscosity generally behaviored in an opposite manner to the sedimentation density, i.e., high sedimentation gave low high-shear viscosity, indicative of low order structure formation in the suspended particles. Shear rate rheology in shear rate of $2-300\;sec^{-1}$ showed a shear thinning and its onset began at similar shear rate (${\sim}100\;sce^{-1}$), regardless of solid loading.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.29-36
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• 2004

A flexible packaging scheme, which includes chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending tests and finite element analysis. Thinned silicon chips (t<30 $\mu\textrm{m}$) are fabricated by chemical etching process to avoid possible surface damages on them. And the chips are stacked directly on $Kapton^{Kapton}$film by thermal compressive bonding. The low height difference between the thinned silicon chip and $Kapton^{Kapton}$film allows electroplating for electrical interconnection method. Because the 'Chip' is embedded in the flexible substrate, higher packaging density and wearability can be achieved by maximized usable packaging area.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.3 s.180
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• pp.56-60
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• 2006

A high-resolution shadow mask, or called a nanostencil was fabricated for high resolution lithography. This high-resolution shadowmask was fabricated by a combination or MEMS processes and focused ion beam (FIB) milling. 500 nm thick and $2{\times}2mm$ large membranes wore made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 70 nm could be made into the membrane. By local deposition through the apertures of nanostencil, nanoscale patterns down to 70 nm could be achieved.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.871-874
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• 2004

Fabrication of a high-resolution shadow mask, or called nanostencil, is presented. This high-resolution shadowmask is fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. 500 nm thick and 2x2 mm large membranes are made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. Subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to high resolution of FIB milling process, nanoscale apertures down to 70 nm could be made into the membrane.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.2
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• pp.245-250
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• 2011

A high-resolution shadow mask, a nanostencil, is widely used for high resolution lithography. This high-resolution shadowmask is often fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. In this study, FIB milling on 500-nm-thin SiN membrane was tested and characterized. 500 nm thick and $2{\times}2$ mm large membranes were made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 60 nm could be made into the membrane. The nanostencil could be used for nanoscale patterning by local deposition through the apertures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.106-108
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• 1994

Electromigration(EM) tests were carried out on Al and Cu films in HV systems to study surface migration. The Al films were made on oxidized silicon wafers by thermal evaporation, in-situ annealed at 300$^{\circ}C$, patterned, and EM tested at 260$^{\circ}C$ and 4.5MA/$\textrm{cm}^2$. SEM observation with back scattered electron mode on the EM tested Al films disclosed that thinning took place under the native Al oxide. In the case of Cu films, tested using in-situ TEM, thinning was also observed at the early stage of void formation even though the thinned areas were much less than those of the Al films.