• 마이크로전자및패키징학회지
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• 제15권2호
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• pp.63-67
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• 2008

전자산업의 소형화와 경량화 추세에 맞추어 최근 집적 칩(IC)이나 패키지를 적층시키는 삼차원 집적화(3D integration) 기술 개발은 차세대 핵심기술로 중요시되고 있다. 본 연구에서는 삼차원 집적화 공정 기술 중 하나인 초박막 실리콘 웨이퍼 연삭(grinding)공정이 웨이퍼 표면에 미치는 영향에 대해서 조사하였다. 실리콘 웨이퍼를 약 $30{\mu}m$과 $50{\mu}m$ 두께까지 연삭한 후, 미세연삭(fine grinding) 단계까지 처리된 시편을 건식 연마(dry polishing) 또는 습식 애칭(wet etching)으로 표면 처리된 시편들과 비교 분석하였다. 박막 웨이퍼 두께는 전계방시형 주사전자현미경과 적외선 분광기로 측정하였고, 표면 특성 분석을 위해선 표면주도(roughness), 표면손상(damage), 경도를 원자현미경, 투과정자현미경 그리고 나노인덴터(nano-indentor)를 이용하여 측정하였다. 표면 처리된 시편의 특성이 표면 처리되지 않은 시편보다 표면주도와 표면손상 등에서 현저히 우수함을 확인 할 수 있었으나, 경도의 경우 표면 처리의 유무에 관계없이 기존의 벌크(bulk)실리콘 웨이퍼와 오차범위 내에서 동일한 것으로 보였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.128-128
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• 2010

In this study, we investigated the evolution and reduction of the surface roughness during the high-speed chemical dry thinning process of Si wafers. The direct injection of NO gas into the reactor during the supply of F radicals from NF3 remote plasmas was very effective in increasing the Si thinning rate, due to the NO-induced enhancement of the surface reaction, but resulted in the significant roughening of the thinned Si surface. However, the direct addition of Ar and N2 gas, together with NO gas, decreased the root mean square (RMS) surface roughness of the thinned Si wafer significantly. The process regime for the increasing of the thinning rate and concomitant reduction of the surface roughness was extended at higher Ar gas flow rates. In this way, Si wafer thinning rate as high as $20\;{\mu}m/min$ and very smooth surface roughness was obtained and the mechanical damage of silicon wafer was effectively removed. We also measured die fracture strength of thinned Si wafer in order to understand the effect of chemical dry thinning on removal of mechanical damage generated during mechanical grinding. The die fracture strength of the thinned Si wafers was measured using 3-point bending test and compared. The results indicated that chemical dry thinning with reduced surface roughness and removal of mechanical damage increased the die fracture strength of the thinned Si wafer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.392-392
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• 2010

In this study, high-speed chemical dry thinning process of Si wafer and evolution of surface roughness were investigated. Direct injection of NO gas into the reactor during the supply of F radicals from $NF_3$ remote plasmas was very effective in increasing the Si thinning rate due to the NO-induced enhancement of surface reaction but thinned Si surface became roughened significantly. Addition of Ar gas, together with NO gas, decreased root mean square (RMS) surface roughness of thinned Si wafer significantly. The process regime for the thinning rate enhancement with reduced surface roughness was extended at higher Ar gas flow rate. Si wafer thinning rate as high as $22.8\;{\mu}m/min$ and root-mean-squared (RMS) surface roughness as small as 0.75 nm could be obtained. It is expected that high-speed chemical dry thinning process has possibility of application to ultra-thin Si wafer thinning with no mechanical damage.

• 한국세라믹학회지
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• 제45권2호
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• pp.99-104
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• 2008

Zeta potential, sedimentation bulk density and rheology in the dispersion system have been studied in terms of solid loading (40-55 vol%), and types of additives. Ammonium polymethacrylate, glycerol, ethoxylated acetylenic diol, and polyvinyl alcohol have been used as the dispersant, cryo-protectant, surfactant, and binder, respectively. Sedimentation density greatly increased upon adding dispersant; the effect was more pronounced with ionic alumina suspension compared with covalent silicon carbide. With further addition of cryo-protectant and surfactant to dispersant, the sedimentation density increased somewhat. The suspension viscosity generally behaviored in an opposite manner to the sedimentation density, i.e., high sedimentation gave low high-shear viscosity, indicative of low order structure formation in the suspended particles. Shear rate rheology in shear rate of $2-300\;sec^{-1}$ showed a shear thinning and its onset began at similar shear rate (${\sim}100\;sce^{-1}$), regardless of solid loading.

• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.71-78
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• 2012

본 논문은 기존의 미세화 경향에 대한 bumpless through-silicon via (TSV)를 적용한 웨이퍼 레벨3차원 적층기술과 그 장점에 대해 소개한다. 3차원 적층을 위한 박막화 공정, 본딩 공정, TSV 공정별로 문제점과 그 해결책에 대해 자세히 설명하며, 특히 $10{\mu}m$ 이하로 박막화한 로직 디바이스의 특성 변화에 대한 결과를 보고한다. 웨이퍼 박막화 공정에서는 기계적 강도 변동 요인, 금속 불순물에 대한 gettering 대책에 대해 논의되며, 본딩 공정에서는 웨이퍼의 두께 균일도를 높이기 위한 방법에 대해 설명한다. TSV형성 공정에서는 누설 전류 발생 원인과 개선 방법을 소개한다. 마지막으로 본 기술을 적용한 3차원 디바이스에 대한 roadmap에 관해 논의할 것이다.

• 마이크로전자및패키징학회지
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• 제11권1호
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• pp.29-36
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• 2004

초 박형 실리콘 칩을 이용하여 실리콘 칩들을 포함한 모듈 전체가 굽힘이 자유로운 유연 패키징 기술을 구현하였으며 bending test와 FEA를 통해 초 박형 실리콘 칩의 기계적 거동을 살펴보았다. 초박형 실리콘 칩(t<30$\mu\textrm{m}$)은 표면손상의 가능성을 배제하기 위해 KOH및 TMAH둥을 이용한 화학적 thinning 방법을 이용하여 제작되었으며 열압착 방식에 의해 $Kapton^{Kapton}$에 바로 실장 되었다. 실리콘칩과 $Kapton^\circledR$ 기판간의 단차가 적기 때문에 전기도금 방식으로 전기적 결선을 이를 수 있었다. 이러한 방식의 패키징은 이러한 공정은 flip chip 공정에 비해 공정 간단하고 wire 본딩과 달리 표면 단차 적어서 연성회로 기판을 비롯한 인쇄회로기판의 표면뿐만 아니라 기판 자체에 삽입이 가능하여 패키징 밀도 증가를 기대할 수 있으며 실질적인 실장 가능면적을 극대화 할 수 있다.

• 한국정밀공학회지
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• 제23권3호
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• pp.56-60
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• 2006

A high-resolution shadow mask, or called a nanostencil was fabricated for high resolution lithography. This high-resolution shadowmask was fabricated by a combination or MEMS processes and focused ion beam (FIB) milling. 500 nm thick and $2{\times}2mm$ large membranes wore made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 70 nm could be made into the membrane. By local deposition through the apertures of nanostencil, nanoscale patterns down to 70 nm could be achieved.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.871-874
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• 2004

Fabrication of a high-resolution shadow mask, or called nanostencil, is presented. This high-resolution shadowmask is fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. 500 nm thick and 2x2 mm large membranes are made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. Subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to high resolution of FIB milling process, nanoscale apertures down to 70 nm could be made into the membrane.

• 한국정밀공학회지
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• 제28권2호
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• pp.245-250
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• 2011

A high-resolution shadow mask, a nanostencil, is widely used for high resolution lithography. This high-resolution shadowmask is often fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. In this study, FIB milling on 500-nm-thin SiN membrane was tested and characterized. 500 nm thick and $2{\times}2$ mm large membranes were made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 60 nm could be made into the membrane. The nanostencil could be used for nanoscale patterning by local deposition through the apertures.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.106-108
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• 1994

Electromigration(EM) tests were carried out on Al and Cu films in HV systems to study surface migration. The Al films were made on oxidized silicon wafers by thermal evaporation, in-situ annealed at 300$^{\circ}C$, patterned, and EM tested at 260$^{\circ}C$ and 4.5MA/$\textrm{cm}^2$. SEM observation with back scattered electron mode on the EM tested Al films disclosed that thinning took place under the native Al oxide. In the case of Cu films, tested using in-situ TEM, thinning was also observed at the early stage of void formation even though the thinned areas were much less than those of the Al films.