• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 한국안광학회지
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• 제19권3호
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• pp.315-322
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• 2014

목적: 4-iodoaniline을 포함한 하이드로젤 콘택트렌즈 기본 재료에 티타늄 실리콘 산화물 나노입자를 첨가하여 친수성 착색 콘택트렌즈의 물리적 및 광학적 특성을 측정하고 제조된 고분자의 자외선 투과율을 측정하여 티타늄 실리콘 옥사이드 나노입자의 자외선 차단 안의료용 렌즈 소재로의 활용도 및 4-iodoaniline만을 기본 콘택트렌즈 재료에 공중합하여 두 실험군의 물성을 비교 분석하였다. 방법: 하이드로젤 렌즈 제조를 위해, HEMA, MA, MMA, 4-iodoaniline, 교차결합제인 EGDMA 및 개시제인 AIBN을 사용하여 공중합 하였다. 또한, 티타늄 실리콘 옥사이드 나노입자는 첨가제로 사용되었다. 중합 후 제조된 콘택트렌즈 재료의 함수율, 굴절률, 접촉각 및 분광투과율 등의 물리적 특성을 측정하였다. 결과: 하이드로젤 렌즈 고분자의 물성을 측정한 결과, 함수율 35.01~ 38.68%, 굴절률 1.4350~1.4418, 접촉각 $34.15{\sim}57.25^{\circ}$ 그리고 UV-B 투과율의 경우 1.0~10.0%의 범위로 나타났다. 또한 첨가제를 사용하지 않은 실험군에서는 함수율 34.0~36.8%, 굴절률 1.4378~1.4420, 접촉각 $40.15{\sim}60.16^{\circ}$ 그리고 UV-B 투과율의 경우 1.8~25.0% 범위의 분포를 나타내었다. 결론: 티타늄 실리콘 옥사이드 나노입자를 첨가한 조합에서 자외선 투과율이 크게 감소하는 것으로 나타났다.

• 대한전자공학회논문지TE
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• 제39권4호
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• pp.335-340
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• 2002

본 논문에서 얇은 실리콘 산화막의 스트레스 유기 누설전류는 나노 구조를 갖는 트랜지스터의 ULSI 실현을 위하여 조사하였다. 인가전압의 온 오프 시간에 따른 스트레스전류와 전이전류는 실리콘 산화막에 고전압 스트레스 유기 트랩분포를 측정하기 위하여 사용하였다. 스트레스전류와 전이전류는 고스트레스 전압에 의해 발생된 트랩의 충방전과 양계면 가까이에 발생된 트랩의 터널링에 기인한다. 스트레스 유기 누설전류는 전기적으로 기록 및 소거를 실행하는 메모리 소자에서 데이터 유지 능력에 영향이 있음을 알았다. 스트레스전류, 전이전류 그리고 스트레스 유기 누설전류의 두께 의존성에 따른 산화막 전류는 게이트 면적이 10/sup －3/㎠인 113.4Å에서 814Å까지의 산화막 두께를 갖는 소자에서 측정하였다. 스트레스 유기 누설전류, 스트레스전류, 그리고 전이전류는 데이터 유지를 위한 산화막 두께의 한계에 대해 연구 조사하였다.

• 한국표면공학회지
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• 제51권3호
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• pp.185-190
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• 2018

Dopant-free silicon heterojunction solar cells using Transition Metal Oxide(TMO) such as Molybdenum Oxide($MoO_X$) and Vanadium Oxide($V_2O_X$) have been focused on to increase the work function of TMO in order to maximize the work function difference between TMO and n-Si for a high-efficiency solar cell. One another way to increase the work function difference is to control the silicon wafer resistivity. In this paper, dopant-free silicon heterojunction solar cells were fabricated using the wafer with the various resistivity and analyzed to understand the effect of n-Si work function. As a result, it is shown that the high passivation and junction quality when $V_2O_X$ deposited on the wafer with low work function compared to the high work function wafer, inducing the increase of higher collection probability, especially at long wavelength region. the solar cell efficiency of 15.28% was measured in low work function wafer, which is 34% higher value than the high work function solar cells.

• 한국표면공학회지
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• 제55권3호
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• pp.143-155
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• 2022

Ceramic oxide layers successfully were formed on the surface of cast Al alloys with high Si contents using plasma electrolytic oxidation (PEO) process in electrolytes containing Na₂SiO₃, NaOH, and additives. The microstructure of the oxide layers was systematically analyzed using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM), X-ray diffraction patterns (XRD), and energy X-ray dispersive spectroscopy (EDS). XRD analysis indicated that the PEO untreated high-silicon Al alloys (i.e., 17.1 and 11.7 wt.% Si) consist of Al, Si and Al₂Cu phases whereas Al₂Cu phase selectively disappeared after PEO treatment. PEO process yielded an amorphous oxide layer with few second phases including γ-Al₂O₃ and Fe-rich phases. The corrosion behaviors of high-silicon Al alloys treated by PEO process were investigated using electrochemical impedance spectroscopy (EIS) and other electrochemical techniques (i.e., open circuit potential and polarization curve). Electroanalytical studies indicated that high-silicon Al alloys treated by PEO process have greater corrosion resistance than high-silicon alloys untreated by PEO process.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 제35회 춘계학술대회
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• pp.310-316
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• 2002

In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1{\mu}m$ in coating thickness. AISI 52100 steel ball was used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction (XRD). Auger electron spectroscopy (AES), scanning electron microscopy (SEM) and sliding tests.

• 한국세라믹학회지
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• 제39권7호
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• pp.693-698
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• 2002

반응소결 탄화규소의 잔류 실리콘 양을 최소화하기 위해 3성분계 탄화규소 분말을 혼합하여 최밀 충전 반음소결 탄화규소를 제조하였다. 기지상의 충전밀도 증가로 인해 반응소결 중 실리콘의 불완전 침윤이 발생하였으며, 이로 인한 잔류 기공은 조대 탄화규소 입자의 표면을 따라 존재함을 확인하였다. 불완전 침윤은 승온 중 분해되지 않고 남은 산화물이 실리콘의 용융 온도 이상에서 분해되어 생긴 고립기공에 의한 것으로 확인되었다. 기지상의 표면에 존재하리라 여겨지는 산화물을 제거하기 위해 침윤전 열처리 및 부식처리를 통해 완전침윤을 달성하였다.

• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.125-130
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• 2000

Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.

• 한국재료학회지
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• 제14권1호
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• pp.9-12
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• 2004

Metallic impurities, such as Fe, Cu, and Au, become generation and recombination centers for minority carriers when combined with oxide precipitates or silicon self-interstitial clusters. As these centers may cause leakage and discharge in silicon devices, their prevention through gettering of the metallic impurities is an important issue. In this article, key aspects of intrinsic gettering, such as oxygen control, wafer cleaning, device area denudation, and bulk oxygen precipitation are discussed, and a practical method of implementing intrinsic gettering is outlined.