• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.121-125
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• 2011

Ribbon silicon solar cells have been investigated because they can be produced with a lower material cost. However, it is very difficult to get good texturing with a conventional acid solution. To achieve high efficiency should be minimized for the reflectance properties. In this paper, acid vapor texturing and anti-reflection coating of $SiN_x$ was applied for EFG Ribbon Si Wafer. P-type ribbon silicon wafer had a thickness of 200 ${\mu}m$ and a resistivity of 3 $\Omega-cm$. Ribbon silicon wafers were exposed in an acid vapor. Acid vapor texturing was made by reaction between the silicon and the mixed solution of HF : $HNO_3$. After acid vapor texturing process, nanostructure of less than size of 1 ${\mu}m$ was formed and surface reflectance of 6.44% was achieved. Reflectance was decreased to 2.37% with anti-reflection coating of $SiN_x$.

• 한국재료학회지
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• 제25권4호
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• pp.196-201
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• 2015

This paper presents the impact of partial shading on $CuIn_xGa_{(1-x)}Se_2(CIGS)$ photovoltaic(PV) modules with bypass diodes. When the CIGS PV modules were partially shaded, the modules were under conditions of partial reverse bias. We investigated the characterization of the bypass diode and solar cell properties of the CIGS PV modules when these was partially shaded, comparing the results with those for a crystalline silicon module. In crystalline silicon modules, the bypass diode was operated at a partial shade modules of 1.67 % shading. This protected the crystalline silicon module from hot spot damage. In CIGS thin film modules, on the other hand, the bypass diode was not operated before 20 % shading. This caused damage because of hotspots, which occurred as wormlike defects in the CIGS thin film module. Moreover, the bypass diode adapted to the CIGS thin film module was operated fully at 60% shading, while the CIGS thin film module was not operated under these conditions. It is known that the bypass diode adapted to the CIGS thin film module operated more slowly than that of the crystalline silicon module; this bypass diode also failed to protect the module from damage. This was because of the reverse saturation current of the CIGS thin film, $1.99{\times}10^{-5}A/cm^2$, which was higher than that of crystalline silicon, $8.11{\times}10^{-7}A/cm^2$.

• Biotechnology and Bioprocess Engineering:BBE
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• 제8권4호
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• pp.252-256
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• 2003

In this paper we describe the status of a silicon-based microelectrode for neural recording and an advanced neural interface. We have developed a silicon neural probe, using a combination of plasma and wet etching techniques. This process enables the probe thickness to be controlled precisely. To enhance the CMOS compatibility in the fabrication process, we investigated the feasibility of the site material of the doped polycrystalline silicon with small grains of around 50 nm in size. This silicon electrode demonstrated a favorable performance with respect to impedance spectra, surface topography and acute neural recording. These results showed that the silicon neural probe can be used as an advanced microelectrode for neurological applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.241-241
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• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• 한국전기전자재료학회논문지
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• 제20권2호
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• pp.101-105
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• 2007

We have synthesized silicon nanowires by using RFCVD(Radio Frequency Chemical Vapor Deposition) system on Au deposited p-type Si(100) wafers, and investigated their physical and electrical properties. The silicon nanowires had been grown in the atmospheres of $H_{2},\;N_{2}\;and\;SiH_{4}$ at 10 Torr at the substrate temperatures of $700{\pm}5^{\circ}C\;and\;810{\pm}5^{\circ}C$ respectively. FE-SEM analysis revealed that diameters of the silicon nanowires are $50{\sim}60nm$ with the length of several ${\mu}m$. XRD analysis showed that the growth direction of the nanowires is Si[111]. Field emission characteristics showed that the turn-of voltages at the current of $0.01\;mA/cm^{2}$ are $10\;V/{\mu}m\;and\;8.5\;V/{\mu}m$ for the wires grown at $700{\pm}5^{\circ}C\;and\;810{\pm}5^{\circ}C$, respectively.

• 한국전기전자재료학회논문지
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• 제24권7호
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.19-20
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• 2006

Two methods that can reduce reflectance in solar cells are surface texturing and anti-reflection coating. Wet chemical etching is a typical method that surface texturing of multi-crystalline silicon. Wet chemical etching methods are the acid texturization of saw damage on the surface of multi-crystalline silicon or double-step chemical etching after KOH saw damage removal too. These methods of surface texturing are realized by chemical etching in acid solutions HF-$HNO_3$-$H_2O$. In this solutions we can reduce reflectance spectra by simple process etching of multi-crystalline silicon surface. We have obtained reflectance of 27.19% m 400~1100nm from acidic chemical etching after KOH saw damage removal. This result is about 7% less than just saw damage removal substrate. The surface morphology observed by microscope and scanning electron microscopy (SEM).

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 한국세라믹학회지
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• 제47권6호
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• pp.572-577
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• 2010

Reaction-bonded $Si_3N_4$ has cost-reduction merit because inexpensive silicon powder was used as a start material. But its density was not so high enough to be used for structural materials. So the sintered reaction-bonded $Si_3N_4$techniques were developed to solve the low density problem. In this study the sintered reaction-bonded $Si_3N_4$ manufacturing method by using polymer precursor which recently attained significant interest owing to the good shaping and processing ability was proposed. The formations, properties of reaction-bonded $Si_3N_4$ from silicon and polysilazane mixture were investigated. High density reaction-bonded $Si_3N_4$ was manufactured from silicon and silicon-containing preceramic polymers and post-sintering technique. The mixtures of silicon powder and polysilazane were prepared and reaction sintered in $N_2$ atmosphere at $1350^{\circ}C$ and post-sintered at 1600~$1950^{\circ}C$. Density and phase were analyzed and correlated to the resulting material properties.