• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.76-84
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• 1992

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.

• Journal of Adhesion and Interface
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• v.9 no.4
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• pp.30-33
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• 2008

Two polymeric interfaces with single component homo-polymers were prepared to control the orientation of block copolymer thin-film nanostructures. Poly(4-acetoxy styrene) (OH-PAS) and poly(4-methoxy styrene) (OH-PMS) which have the average chemical composition of polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) were precisely synthesized through nitroxide-mediated radical polymerization. After dehydration reactions between above polymers and SiOx layers of silicon wafers, the polymer-modified interface induced partial (30%) vertical orientation of PS-b-PMMA thin film in the case of OH-PMS and wholly parallel orientation in the case of OH-PAS. Chemical compositions of polymeric interface layers are regarded as the key parameter to control the orientation of nanostructures of block copolymer thin film.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.315-315
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• 2006

A variable surface coating with the potential to fulfill the requirements of industry will be presented. Via controlled radical polymerization methods from a functionalized Polymethylsilsesquioxane delivers an inorganic-organic block copolymer, which can be easily modified and tuned for different applications. Spin coated or dip coated on various substrates show promising results. By using different block copolymers the contact angle on a silicon wafer can be varied in a range of $90^{\circ}\;up\;to\;145^{\circ}$ After curing and complete condensation a perfect adhesion on glasses, plastics and metals is achieved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.39-46
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• 1994

CMOS LCD driving circuits using poly-Si TFT have been designed and basic blocks including test patterns have been fabricated. Column driver drives the pixels by block because polu-Si TFT can not operate at the speed of video signal. Row driver has mode selection circuit which can select a mode between interlacing mode and non-interlacing mode. Experimental results show shift register can operate at 1MHz colck frequency with 4pF load.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.789-790
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.1157-1158
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• 2011

• Macromolecular Research
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• v.12 no.1
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• pp.127-133
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• 2004

We have studied the surface micelle formation of polystyrene-b-poly(2-vinyl pyridine) (PS-b-P2VP) at the air-water interface. A series of four PS-b-P2VPs were synthesized by anionic polymerization, keeping the PS block length constant (28 kg/㏖) and varying the P2VP block length (1, 11, 28, or 59 kg/㏖). The surface pressure-area ($\pi$-A) isotherms were measured and the surface morphology was studied by atomic force microscopy (AFM) after Langmuir-Blodgett film deposition onto silicon wafers. At low surface pressure, the hydrophobic PS blocks aggregate to form pancake-like micelle cores and the hydrophilic P2VP block chains spread on the water surface to form a corona-like monolayer. The surface area occupied by a block copolymer is proportional to the molecular weight of the P2VP block and identical to the surface area occupied by a homo-P2VP. It indicates that the entire surface is covered by the P2VP monolayer and the PS micelle cores lie on the P2VP monolayer. As the surface pressure is increased, the $\pi$-A isotherm shows a transition region where the surface pressure does not change much with the film compression. In this transition region, which displays high compressibility, the P2VP blocks restructure from the monolayer and spread at the air-water interface. After the transition, the Langmuir film becomes much less compressible. In this high-surface-pressure regime, the PS cores cover practically the entire surface area, as observed by AFM and the limiting area of the film. All the diblock copolymers formed circular micelles, except for the block copolymer having a very short P2VP block (1 kg/㏖), which formed large, non-uniform PS aggregates. By mixing with the block copolymer having a longer P2VP block (11 kg/㏖), we observed rod-shaped micelles, which indicates that the morphology of the surfaces micelles can be controlled by adjusting the average composition of block copolymers.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.13-17
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• 2006

Dense and periodic arrays of holes and tungsten none dots were fabricated on silicon oxide and silicon. The holes were approximately 25 nm wide, 40 nm deep, and 60 nm apart. To obtain nano-size patterns, self-assembling resists were used to produce layer of hexagonally ordered parallel cylinders of polymethylmethacrylate(PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS mask for pattern transfer. The silicon oxide was removed by fluorine-based reactive ion etching(RIE). Selectively deposited tungsten nano dots were formed inside nano-sized trench by using a low pressure chemical vapor deposition(LPCVD) method. Tungsten nano dot and trenched silicon sizes were 26 nm and 30 nm, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.49-57
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• 2002

Including RF Package inductance, substrate coupling through conductive silicon(Si)-substrate is modeled and quantitatively characterized. 2-port substrate coupling model is extended for the characterization of multi-port substrate coupling between digital circuit block and analog/RF circuit block. Furthermore, scalable parameter extraction model is developed. Multi-port substrate coupling can be investigated by linearly superposing a frequency-dependent 2-port substrate coupling model using scalable parameters. In addition, Substrate coupling including RF package inductance effect is quantitatively investigated. It is shown that package effect increases substrate coupling and shifts a characteristic frequencies(i.e., poles) to the higher frequency range. The proposed methodology can be efficiently used to the mixed-signal circuit performance verification.