• Title/Summary/Keyword: Signal processing circuit

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Analyzing of CDTA using a New Small Signal Equivalent Circuit and Application of LP Filters (새로운 소신호 등가회로를 활용한 CDTA의 해석 및 저역통과 필터설계)

  • Bang, Junho;Song, Je-Ho;Lee, Woo-Choun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.12
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    • pp.7287-7291
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    • 2014
  • A CDTA (current differencing transconductance amplifier) is an active building block for current mode analog signal processing with the advantages of high linearity and a wide frequency bandwidth. In addition, it can generate a stable voltage because all the differencing input current flows to the grounded devices. In this paper, a new small signal equivalent circuit is proposed to analyze a CDTA. The proposed small signal equivalent circuit provides greater precision in analyzing the magnitude and frequency response than its previous counterparts because it considers the parasitic components of the input, internal and output terminal. In addition, observations of the changes made in various devices, such as the resistor (Rz) confirmed that those devices heavily influence the characteristics of CDTA. The designed parameters of the proposed small signal equivalent circuit of the CDTA provides convenience and accuracy in the further design of analog integrated circuits. For verification purposes, a 2.5 MHz low pass filter was designed on the HSPICE simulation program using the proposed small signal equivalent circuit of CDTA.

The A/D Converter for Low Power Multifunctional Sensor System (저전력 다기능 센서시스템 A/D Converter)

  • 박창규;김정규;이지원;김수성;최규훈
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1019-1022
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    • 2003
  • This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

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The Performance Analysis of The Digital Trunk Circuit Processor in The TDX-1A (TDX-1A의 디지틀 중계선 정합 프로세서의 성능분석)

  • Ahn, Jee-Hwan;Park, Kwang-Ro;Lee, Yong-Kyun
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.510-513
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    • 1988
  • This paper describes an effective trunk loop signal processing method and analyzes execution time of program in the DTCP(Digital Trunk Circuit Processor) in the TDX-1A digital switching system. To predict a maximum trunk capacity, also analyzes to Z80A system clock(4Mbit/s, 2.5Mbit/s) and scanning period(8mS,5mS) respectively.

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Detection of Stator Winding Inter-Turn Short Circuit Faults in Permanent Magnet Synchronous Motors and Automatic Classification of Fault Severity via a Pattern Recognition System

  • CIRA, Ferhat;ARKAN, Muslum;GUMUS, Bilal
    • Journal of Electrical Engineering and Technology
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    • v.11 no.2
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    • pp.416-424
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    • 2016
  • In this study, automatic detection of stator winding inter-turn short circuit fault (SWISCFs) in surface-mounted permanent magnet synchronous motors (SPMSMs) and automatic classification of fault severity via a pattern recognition system (PRS) are presented. In the case of a stator short circuit fault, performance losses become an important issue for SPMSMs. To detect stator winding short circuit faults automatically and to estimate the severity of the fault, an artificial neural network (ANN)-based PRS was used. It was found that the amplitude of the third harmonic of the current was the most distinctive characteristic for detecting the short circuit fault ratio of the SPMSM. To validate the proposed method, both simulation results and experimental results are presented.

Improvement of Time-Delay of the Analog Viterbi Decoder through Minimizing Parasitic Capacitors in Layout Design (아날로그 비터비 디코더에 있어서 기생 cap성분 최소화 layout 설계에 의한 신호전파 지연 개선)

  • Kim, In-Cheol;Kim, Hyun-Jung;Kim, Hyong-Suk
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.196-198
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    • 2007
  • A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

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Health and Wellness Monitoring Using Intelligent Sensing Technique

  • Meng, Yao;Yi, Sang-Hoon;Kim, Hee-Cheol
    • Journal of Information Processing Systems
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    • v.15 no.3
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    • pp.478-491
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    • 2019
  • This work develops a monitoring system for the population with health concerns. A belt integrated with an on-body circuit and sensors measures a wearer's selected vital signals. The electrocardiogram sensors monitor heart conditions and an accelerometer assesses the level of physical activity. Sensed signals are transmitted to the circuit module through digital yarns and are forwarded to a mobile device via Bluetooth. An interactive application, installed on the mobile device, is used to process the received signals and provide users with real-time feedback about their status. Persuasive functions are designed and implemented in the interactive application to encourage users' physical activity. Two signal processing algorithms are developed to analyze the data regarding heart and activity. A user study is conducted to evaluate the performance and usability of the developed system.

A Study on the Signal Processing and Robust Control for a 3-DOF Active Vibration Isolator (3자유도 능동형 제진 시스템을 위한 신호처리 및 강인제어에 관한 연구)

  • Moon, Jun-Hee;Kim, Hwa-Soo;Pahk, Heui-Jae
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2006.05a
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    • pp.153-156
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    • 2006
  • The vibration isolation system is a system that attenuates the vibration transmitted from surroundings by using external energy supply like electricity and feedback and/or feedforward functions. Such a system needs stiff structure to make precise positioning without ripple within a certain bandwidth. So, a horizontal and rotary arrangement of the actuation module is suggested by using lever linkage. Modeling and kinematic formulation are completed and system identification is accomplished to tune the design variables accurately. The vibration isolation control is performed by mu-synthesis with the uncertainties in design variables. Low frequency signal enhancement circuit and saturation proof integration algorithm are devised to use seismic sensors for displacement control. This overall system shows good disturbance rejection performance.

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A Study On Bar-Code Signal Processing System (바-코드 신호처리 시스템에 관한 연구)

  • Ihm, J.T.;Eun, J.J.;Park, H.K.
    • Proceedings of the KIEE Conference
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    • 1987.07a
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    • pp.61-63
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    • 1987
  • In this paper, we develope a system which can perform signal processing for bar-code laser scanner. This system is composed of optical detector and preprocessor. The former detects the diffused light and converts it into TTL lebel output. The latter discriminator valid data from various raw data and transmits data to micro-processor. The preprocessor consists of edge transition detector, latch signal generator, module counter, register array, adder array, and buffer memory control circuit etc..

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A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

  • Tanaka, Tomoki;Kishine, Keiji;Tsuchiya, Akira;Inaba, Hiromi;Omoto, Daichi
    • IEIE Transactions on Smart Processing and Computing
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    • v.5 no.3
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    • pp.207-214
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    • 2016
  • Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

Signal Processing of Capacitive Load and Gap Measurement with High Precision Using Surface Acoustic Wave Device (표면 탄성파 장치를 이용한 용량성 부하의 신호처리 및 이를 이용한 초정밀 간극 측정)

  • Kim, Jae-Geun;Lee, Taek-Joo;Lim, Soo-Cheol;Park, No-Cheol;Park, Young-Pil;Park, Kyoung-Soo
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2009.10a
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    • pp.376-380
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    • 2009
  • Surface acoustic wave (SAW) device is widely used as a bandpass filter, a chemical or physical sensor, and an actuator. In this paper, we propose the capacitive gap measurement system with high precision through the signal processing using SAW device. The research process is mainly composed of theoretical part and experimental part. In theoretical part, equivalent circuit model was used to simulate the SAW response by the change of capacitance. In experimental part, commercialized capacitor was used to see the SAW response by the change of load capacitance. After that, gap adjustment system was made physically and the SAW response by the change of gap which caused the capacitance change was measured. And resolution and stroke was decided comparing the signal change and basic measurement noise level.

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