• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.1
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• pp.94-102
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• 2018

In this paper, the wideband mono-pulse radar using AGC and limiter is designed. The output response characteristics of the mono-pulse radar using AGC and limiter are analyzed, respectively. In addition, the output response for jamming input signals is analyzed. The range tracking loop in the mono-pulse radar has robust output response to the noise jamming input signal. Although the output settling response of the AGC-based mono-pulse radar is larger than that of the limiter-based mono-pulse radar, the AGC-based mono-pulse radar has robustness to the noise jamming input signal due to feedback loop.

• Korean Journal of Optics and Photonics
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• v.8 no.5
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• pp.426-430
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• 1997

A signal processor is implemented to verify the possibility of a closed-loop signal processing for the open-loop fiber-optic gyroscope (FOG). As an all-digital implementation of phase tracking scheme, it does analog-to digital conversion of the detector output and signal processing all-digitally thereafter for a noise-immune FOG signal processor. It has a potential of 36-bits resolution in the $2\pi$ range which is best in the number and sets no limit in the magnitude of the phase shift. The new signal processor was tested on an all-fiber gyroscope and turned out to have a resolution of $3\mu$rad(corresponds to 0.74 deg/hr), which is good enough to measure the Earth's rotation rate.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.179-181
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• 1987

In this paper, a self-tuning controller design is proposed by using pole-zero placement method and considering a system time delay. To got better tracking for the generalized self-tuning controller, pole placement method for the closed loop system and zero placement method for the error transfer function are Introduced. The proposed method shows better efficiency than pole placement method for minimizing tracking error. Simulation gives good results in tie reference signal tracking.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.8
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• pp.893-901
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• 1992

In this paper, we propose a new resolver-to digital(R/D) conversion method, in which a bang-bang type phase comparator is employed for fast tracking. We eliminate from the R/D conversion loop the low-pass filter which is needed to reject carrier signal and noise. Instead, we employ two prefilters outside the R/D conversion loop that take the role of the low-pass filter. Thereby, we can construct a fast and accurate tracking R/D converter. Some simulation and experimental results as well as mathematical performance analysis are presented to demonstrate the superior tracking performance of our R/D converter over conventional tracking R/D converters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.871-880
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• 1999

In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1421-1432
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• 1994

The optimum design and performance of noncoherent TDL considering the effect of distortions due to the IF bandpasss filters are described. NRZ data and ideal filter is presumed in the simulation. The optimum filter bandwidth is calculated in the sense of minimizing the loop's squaring loss, which is equivalent to minimizing the loop's tracking jitter for a given data rate and data signal-to-noise ratio. As a result, the optimum filter bandwidth depends on the signal-to-noise ratio, and is obtained in the range of about 1-2 times of the data rate.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.377-383
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• 2002

An all-digital closed-loop (ADCL) signal processor for an open-loop FOG was developed to replace the analog circuitry of a Digital Phase Tracking (DPT) signal processor with new digital circuitry. When the ADCL signal processor without a stabilizer for fiber phase modulator (FPM) was attached to the FOG, temperature drift of FOG was about 0.26$\mu$rad/$^{\circ}C$, which makes the FOG unusable in medium or higher-grade applications. This drift was due to variations of phase modulation amplitude and phase delay of the FPM. The stabilizer controls its phase modulation amplitude and phase delay by regulating the ratio of harmonics of the FOG output. Thus, the stabilizer reduces the drift of the FOG to negligible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.857-864
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• 1998

The infuluence of Doppler effects on the tracking performance of a noncoherent second-order delay locked loop (DLL) operating on a data modulated signal is investigated. For the perfoermance analysis we consider the tracking accuracy (steady state error and jitter) of the linear DLL and the reliability of the nonlinear loop. The nonlinear analysis concerning the loop reliability makes use of an asympototic expansion for the MTLL(mean time to lose lock) which has been derived by applying the singular perturbation method. In particular, we give optimal loop parameters and the optimal bandwidth of the bandpass filter in the loop arms to achieve a maximum MTLL. Since Doppler effects can be producesd comparatively in LEO system, we can espect the more reliable DLL loop design. by using the results of the circuit simulation, the delay lock loop is synthesized in FPGA, and verified to get the GPS data from the STR-2770 GPS simulator system. So, the synthesized logic circuit is shown be accurately performed.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.5
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• pp.615-621
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• 2009

Since GPS receivers and INS algorithms do not work properly in the spinning vehicles due to change of the GPS signal and excess of the measurement limitation of the gyroscope, conventional GPS/INS integrated navigation systems do not provide accurate navigation outputs. This paper proposes a design method for GPS/INS integrated navigation systems of spinning vehicles. A special GPS receiver with a signal tracking loop for changed GPS signal caused by spinning and an INS with a roll estimation method are configured and the conventional integration filter is combined. The proposed method was verified through comparison of the navigation results. The result of the proposed method for the spinning vehicle was similar to that of the conventional navigation system without spinning.