• Journal of the Korean Society for Railway
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• v.5 no.2
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• pp.55-60
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• 2002

This study proposes the post-processor simulator construction of ultrasonic signal for integrity evaluation of railway truck. For these purposes, the ultrasonic signals for defects(crack) of weld zone in frames are acquired in the type of time series data and echo strength. The detection of the natural defects in railway truck is performed using the characteristics of echodynamic pattern in ultrasonic signal. The constructed post-processor simulator agree fairly well with the measured results of test block(defect location, beam propagation distance, echo strength, etc). Proposed post-processor simulator construction of ultrasonic in this study can be used for the integrity evaluation of railway truck.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.82-90
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• 2011

An accurate signal integrity verification method based on high-frequency measurements is proposed. For practical transmission lines that require a package process, process variations metal roughness and skin effects and boundary conditions may have deteriorative effects on circuit performance. These effects are represented in terms of parameters that can be readily utilized for field-solver. Thereby a more accurate signal integrity verification using field-solver can be achieved. It is shown that in both single and coupled lines the signal transients using the proposed method have excellent agreement with the measurement data.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.125-132
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• 2015

PCI Express is high-speed point-to-point serial protocol, the system is designed by analysing loss and jitter through Eye Diagram. It is necessarily analyzing high speed serial signals when the PCI Express Gen3 which has 8Gbps physical signal speed is designed especially. This paper deals with topology extraction, channel analysis, extraction of s-parameters and system signal integrity simulation within transceiver buffer models through PCI Express Gen3 server connecting switch system design. Optimal parameters of transmitter buffer equalizer are found through solution space simulation of de-emphasis and preshoot parameters to compensate channel loss.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.275-278
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• 2000

As the operating frequency of digital modules in network system becomes fast, integrity of signals between modules is regarded as a important factor in high speed system design. To guarantee the signal integrity, many factors that deteriorate quality of signal should be considered. In this paper, we survey many factors which be considered while in designing and imp]ementing the backplane for high speed router and analyze the simulation result and experimental result.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.452-460
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• 2021

As the global electric vehicle (EV) market expands, eco-friendly EV that complement performance and safety problems continue to be released and the market is growing. However, in the case of EVs, the inconvenience of charging, safety problems such as electric shock, and electromagnetic interference (EMI) problems caused by the interlocking of various electronic components are problems that must be solved in EVs. The use of wireless power transmission technology can solve the problem of safety by not dealing with high current and high voltage directly and solving the inconvenience of charging EVs. In this paper, in order to reduce EMI a wireless charging control module, which is a key electronic component of WPT of EV. EMI reduction was designed through simulation of problems such as resonance and impedance that may occur in the power supply and signal distortion between high-speed communication that may occur in the signal part. Therefore, through the EMI reduction design with power integrity and signal integrity, the WPT wireless charging control module for electric vehicles reduces 10 dBu V/m and 15 dBu V/m, respectively, in 800 MHz to 1 GHz bands and 1.5 GHz bnad.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1263-1270
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• 2000

The operation frequency of High-speed Communication System becomes very fast with the advanced technology of VLSI chips and system implementation. There may exist various types of noise sources degrading the signal integrity in this system. The present main system is made of backplane, so faults can be brought whenever a board is removed, replaced or added. This backplane boards testing is a very important process to verify the operation of system. firstly, we model the effects of the internal noises in the High-speed Communication System to the signal line and propose a new design method to minimize these effects. For the design methodology, we derive the characterization value for each mode land them construct the optimal simulation model. We compare the result of own proposing method with that fo the existing methods, through simulation and show that the quality of High-speed Communication System is significantly enhanced. Secondary our proposing BIST for the Backplane Boards Testing is designed to guarantee that there is no fault in the high-speed communication system.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.77-82
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• 2006

Integrity plays a fundamental role in the feasibility of 'liability critical' applications. Road charging, e.g. road tolling in urban zones or on highways, represents a series of liability critical applications where a guarantee in integrity could be a true enabler: being the mechanism that prevents the incorrect charging of users and enabling the advancement of these applications using GNSS such as Galileo and EGNOS that provide integrity mechanisms. However, the integrity of the end user position is not guaranteed by the EGNOS and Galileo integrity services alone as provided. Algorithms have been developed to supply a guarantee on the performance attainable at the user level through the provision of a horizontal protection level that responds to local user conditions such as multipath or interference. In addition, an application has been developed that implements road charging mechanisms based on the availability of user-level integrity. Results obtained show that the user-level integrity algorithms provided the required level of integrity guarantee and granularity of the horizontal protection levels necessary for executing urban and rural (highway) road charging. In addition, the road charging application developed shows that the current application domain requirements can be met through the provision of guaranteed integrity and that further reductions in the horizontal protection levels along with increased signal availability will enable future road charging modalities.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.726-735
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• 2014

In accordance with 4K UHD(Ultra High Definition) LCD television's higher resolution and data expansion, LCD TV had to face problems such as increasing numbers of cables and tangible skews problems among cables. The V-by-One HS is a new interface technology in the path between the image processing IC and timing control (TCON) board. The variable speed from 600 Mbps to 3.75 Gbps effectively meets the requirements of various different pixel rates. In this paper, we use the V-by-One HS interface to illustrate our proposed simulation method of frequency resonance mode and PCB design approach to model the effects of signal integrity for high speed video signal using an IBIS models.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.188-193
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• 2010

In this paper, SI(Signal Integrity) characteristic of the 4-layer PCB(Printed Circuit Boards) with a through-hole via was analyzed by impedance mismatching between the through-hole via and the transmission line, and deterioration of clock pulse response characteristic due to the P/G plane resonances which are generated between the power and the ground plane. The minimized impedance mismatching between the through-hole via and the transmission line for the improving of SI characteristic is confirmed by the TDR(Time Domain Reflector) simulation and lumped element modeling of the through-hole via. And the cancellation method of P/G plane resonances for improvement of the SI characteristic is represented by simulation result.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.