고주파 전송선 회로의 실험적 고찰을 통한 정확한 시그널 인테그러티 검증

Accurate Signal Integrity Verification of Transmission Lines Based on High-Frequency Measurement

  • 신승훈 (한양대학교 전자컴퓨터공학) ;
  • 어영선 (한양대학교 전자컴퓨터공학)
  • Shin, Seung-Hoon (Department of Electrical and Computer Engineering, Hanyang University) ;
  • Eo, Yung-Seon (Department of Electrical and Computer Engineering, Hanyang University)
  • 투고 : 2011.03.07
  • 심사 : 2011.05.16
  • 발행 : 2011.07.25

초록

본 논문은 실험적 고찰을 통해 고주파 전송선 회로의 시그널 인테그러티를 정확하게 검증하는 방법을 제시하였다. 패키지 공정을 이용하여 제조한 배선의 공정편차, 표면 거칠기 효과, 표피 효과, 시뮬레이션을 위한 경계조건 등은 시뮬레이션의 정확도에 상당한 영향을 끼친다. 이러한 영향을 장해석기(HFSS)에 적용할 수 있는 변수로 변환하여 보다 정확하게 시그널 인테그러티를 검증 할 수 있도록 한다. 단일 신호선과 두 개의 전자기적으로 결합된 신호선에서의 신호 천이 특성을 측정 데이터와 제안하는 방법의 시뮬레이션 결과와 비교를 통해 제안한 방법의 정확성을 검증하였다.

An accurate signal integrity verification method based on high-frequency measurements is proposed. For practical transmission lines that require a package process, process variations metal roughness and skin effects and boundary conditions may have deteriorative effects on circuit performance. These effects are represented in terms of parameters that can be readily utilized for field-solver. Thereby a more accurate signal integrity verification using field-solver can be achieved. It is shown that in both single and coupled lines the signal transients using the proposed method have excellent agreement with the measurement data.

키워드

참고문헌

  1. "International technology roadmap for semiconductors," SIA, Rep., 2006.
  2. R. R. Tummala, "SOP: What is it and why? A new microsystem-integration techology paradaigm Moor's law for system integration of miniaturized convergent systems of the next decade," IEEE Trans. Advanced Packaging, vol. 27, no. 2, pp. 214-249, May. 2004.
  3. V. Kripesh, S. W. Yoon, V. P. Ganesh, N. Khan, M. D. Rotaru, W. Fang, and M. K. Iyer, "Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology," IEEE Trans. Advanced Packaging, vol. 28, no 3, pp. 377-386, Aug. 2005.
  4. A. J. Bhavnagarwala, A. Kapoor, and J. D. Meindl, "Generic models for interconnect delay across arbitrary wire-tree networks," in Proc. IITC., pp. 129-131, 2000.
  5. A. B. Kahng and S. Muddu, "An analytical delay model for RLC interconnects," IEEE Trans. Computer-Aided Design, vol. 16, no. 12, pp. 1507-1514, Dec. 1997. https://doi.org/10.1109/43.664231
  6. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent Elmore delay for RLC trees," IEEE Trans. Computer-Aided Design, vol. 19, no. 1, pp. 83-97, Jan. 2000. https://doi.org/10.1109/43.822622
  7. H. Kim and Y. Eo, "High-frequencymeasurement- based circuit modeling and power/ground integrity evaluation of integrated circuit packages," IEEE Trans. Advanced Packaging, vol. 31, no. 4, pp. 910-918, Nov. 2008. https://doi.org/10.1109/TADVP.2008.2005472
  8. D. Kim and Y. Eo, "S-parameter-based time-domain signal transient and crosstalk noise characterizations of coupled transmission lines," IEEE Trans. Advanced Packaging, vol. 32, no. 1, pp. 152-163, Feb. 2009. https://doi.org/10.1109/TADVP.2008.2004465
  9. W. R. Eisenstadt and Y. Eo, "S-parameter-based IC interconnect transmission line characterization," IEEE Trans. Comp., Hybrids, Manufact. Technol., vol. 15, no. 4, pp. 483-490, Aug. 1992. https://doi.org/10.1109/33.159877
  10. H. T. Vo, C. Davidson, and F. G. Shi, "New effective dielectric constant model for ultra-high speed microstrip lines on multilayer dielectric substrates : effect of conductor-dielectric interphase," in Proc. ECTC., pp.86-89, 2002.