• 전자공학회논문지
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• 제52권4호
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• pp.184-193
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• 2015

TDOA(Time Difference of Arrival) 기반 수동형 전자감시장비는 이격 동작하는 다수의 수신기에서 수신되는 전자파 신호의 펄스도착시간인 TOA(Time of Arrival) 정보를 이용하여 신호원의 공간상 위치를 탐지한다. 수신기 간 이격 거리 대비 신호원에서 방사되는 신호의 PRI(Pulse Repetition Interval)가 크지 않을 경우 TDOA 기반 위치탐지를 위한 각 수신기에서의 동일 펄스쌍 선정에 모호성이 발생될 수 있다. 본 논문에서는 이격 동작하는 각 수신기에서 수신한 펄스들과 신호원간의 순시방향탐지결과인 AOA(Angle of Arrival)를 이용하여 펄스 선택의 모호성을 신호원의 위치와 신호원으로부터 수신한 펄스들과의 TDOA 최적화 문제로 변경하고 이를 유전 알고리즘 기반으로 TDOA 기반 위치탐지 과정에서 발생될 수 있는 동일 펄스선택 모호성을 최소화할 수 있는 새로운 기법을 제안하며, 다양한 모의실험을 통해 제안된 기법의 성능을 분석하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.366-368
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• 2006

Electronic warfare Support(ES) system measures pulse characteristics for received RF signals that received from all directions. ES system discriminates the pulse trains that have a rule, correlationship, continuance from collected data and analyze the characteristics of the data, and identify the emitters by comparison with emitter identification data(EID). Because pulse density is very high and various signal source exists at modem signal environments, high-speed and accurate signal analysis is needed for realtime countermeasure to emitters. Grouping alleviates the load of signal analysis process and supports reliable analysis. In this paper, we suggest an adaptive clustering scheme regarding signal patterns.

• 한국안전학회지
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• 제28권2호
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• pp.26-30
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• 2013

The purpose of this study is to find risk factors by analyzing the operation principle of a photo coupler (P/C) used to remove the noise of electronic devices and establish a base for the performance improvement of developed products. It was found from the P/C circuit analysis of normal products that they were equipped with an electrolytic condenser of $0.1{\mu}F$ to smooth system signals. Due to the epoxy resin packing the external part of the P/C, this study experienced a limit to visually examine the damage to it. It could be seen from the analysis of electric characteristics of the P/C that the forward voltage ($V_f$) and reverse current ($I_r$) were 1.3 V and 10 uA, respectively. In addition, it is required that the breakdown voltage (VCE) between the collector (C) and emitter (E) be maintained at less than 35 V. The and of the damaged product #1 were comparatively good. However, the measurement of was 100.0 uA. From this, it is thought that a short circuit occurred to the internal circuit. Moreover, from the fact that the of the damaged product #2 was open circuit and the measurement of was 0.0 uA, it is thought that the collector and emitter was separated or insulation resistance was significantly high. Furthermore, from the fact that the of the damaged product #3 was open circuit and the measurement of was 0.0 uA, it is thought that the space between the collector (C) and emitter (E) failed to meet the design standard or that they were separated. Therefore, it is thought that fabricating the P/C by increasing the reverse current 10 mA to 50 mA will prevent its malfunction.

• 전자공학회논문지SC
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• 제43권4호
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• pp.45-52
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• 2006

본 연구에서는 위상잡음과 지터(jitter) 특성을 개선한 $5mm{\times}7mm$ 크기의 적층 세라믹 SMD(surface mounted device)형 VCXO를 개발한다. PECL(positive emitter coupled logic) 칩패키지를 발진수정자에 결선한 VCXO는 그 길이 및 패키지 내부의 패턴 등에 의하여 부유인덕턴스 및 기생 커패시턴스가 발생하고, 전원의 반사 및 잡음 발생으로 출력신호의 진폭 감소 및 신호 손실이 발생하여 발진기 성능을 정상적으로 평가할 수 없다. 이러한 신호 손실 및 진폭감소를 방지하기 위해 지그(Jig) 시스템을 개발하고, 이를 통하여 발진기의 정확한 스펙트럼 분석 및 성능을 평가한다. 동작전원은 3.3 V, 주파수 범위 120-180 MHz 및 Q인수는 5K이다.

• 전자공학회논문지D
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• 제34D권7호
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• pp.15-22
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• 1997

A 10Gbit/s limiting amplifier IC for optical transmission system was implemented with AlGaAs HBT (heterojunction bipolar transistor) technology. HBTs with 2x10.mu. $m^{2}$ and 6x20.mu. $m^{2}$ emitter size were used. The HBT structures are based on metal-organic chemical vapor deposition (MOCVD) epitxy and employ a mesa structure with self-aligned emitter/base and sidewall dielectric passivation. IC was designed to support differnetial input and output. Small signal performance of the packaged IC showed 26dB gain and $f_{3dB}$ of 8GHz. A single ouput has 800m $V_{p-p}$ swing with more than 26dB dynamic range. The performance of the limiting amplifier was verified through single mode fiber320km transmission link test.est.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.274-280
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• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• 전자공학회논문지A
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• 제30A권12호
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• pp.51-59
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• 1993

A 4${\times}10^{19}cm^{3}$ carbon-doped base AlGaAs/GaAs HBY was grown using carbontetracholoride(CCl$_4$) by atmospheric pressure MOCVD. Abruptness of emitter-base junction was characterized by SIMS(secondary ion mass spectorscopy) and the doping concentration of base layer was confirmed by DXRD(double crystal X-ray diffractometry). Mesa-type HBTs were fabricated using wet etching and lift-off technique. The base sheet resistance of R$_{sheet}$=550${\Omega}$/square was measured using TLM(transmission line model) method. The fabricated transistor achieved a collector-base junction breakdown voltage of BV$_{CBO}$=25V and a critical collector current density of J$_{O}$=40kA/cm$^2$ at V$_{CE}$=2V. The 50$\times$100$\mu$$^2$ emitter transistor showed a common emitter DC current gain of h$_{FE}$=30 at a collector current density of JS1CT=5kA/cm$^2$ and a base current ideality factor of ηS1EBT=1.4. The high frequency characterization of 5$\times$50$\mu$m$^2$ emitter transistor was carried out by on-wafer S-parameter measurement at 0.1~18.1GHz. Current gain cutoff frequency of f$_{T}$=27GHz and maximum oscillation frequency of f$_{max}$=16GHz were obtained from the measured Sparameter and device parameters of small-signal lumped-element equivalent network were extracted using Libra software. The fabricated HBT was proved to be useful to high speed and power spplications.

• 대한전자공학회논문지SP
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• 제48권6호
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• pp.124-132
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• 2011

현대 전자전에서 레이더 신호 환경은 매우 복잡하고 고밀도화 되어 가고 있다. 이러한 신호로부터 원래의 방사체로 각각 분리하여 분석하고 식별하기 위한 전자전지원을 위해서는 신뢰성있는 신호분석 기법이 요구된다. 본 논문에서는 전자전지원의 신호분석 단계에서 신뢰성을 보장하며 신호처리 비용을 줄일 수 있는 새로운 레이더 신호 그룹화 알고리즘을 제안하였다. 제안된 기법은 주파수 변조 특성에 대한 통계적 분포 특성을 활용하여 수신 신호로부터 커널 밀도 추정 방식을 이용하여 신호 그룹화한다. 제안된 기법에 대해 실험 결과를 통해 우수한 성능을 보유함을 확인하였다.

• 전자공학회논문지D
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• 제35D권4호
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• pp.84-92
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• 1998

A program was developed to analyze the electrical characteristics and harmonic distrotion in a two-dimensional silicon BJT. The finite difference equations of the small signal and its second and thired harmonics for basic semiconductor equations are formulated treating the nonlinearity and time dependence with Volterra series and Taylor series. The soluations for three sets of simultaneous equations were obtained sequantially by a decoupled iteration method and each set was solved by a modified Stone's algorithm. Distortion magins and ac parameters such as input impedance and current gains are calculated with frequency and load resistance as parameters. The distortion margin vs. load resistancecurves show cancellation minima when the pahse of output voltage shifts. It is shown that the distortionof small signal characteristics can be reduced by reducing the base width, increasing the emitter stripe length and reducing the collector epitaxial layer doping concentration in the silicon BJT structure. The simulation program called TRADAP can be used for the design and optimization of transistors and circuits as well as for the calculation of small signal and distortion solutions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.