• Korean Journal of Materials Research
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• v.8 no.10
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• pp.890-897
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• 1998

The direct wafer bonding between n-InP(001) wafer and the ${Si}_3N_4$(200 nm) film grown on the InP wafer by PECVD method was investigated. The surface states of InP wafer and ${Si}_3N_4$/InP which strongly depend upon the direct wafer bonding strength between them when they are brought into contact, were characterized by the contact angle measurement technique and atomic force microscopy. When InP wafer was etched by $50{\%}$ HF, contact angle was $5^{\circ}$ and RMS roughness was $1.54{\AA}$. When ${Si}_3N_4$ was etched by ammonia solution, RMS roughness was $3.11{\AA}$. The considerable amount of initial bonding strength between InP wafer and ${Si}_3N_4$/InP was observed when the two wafer was contacted after the etching process by $50{\%}$ HF and ammonia solution respectively. The bonded specimen was heat treated in $H^2$ or $N^2$, ambient at the temperature of $580^{\circ}C$-$680^{\circ}C$ for lhr. The bonding state was confirmed by SAT(Scannig Acoustic Tomography). The bonding strength was measured by shear force measurement of ${Si}_3N_4$/InP to InP wafer increased up to the same level of PECVD interface. The direct wafer bonding interface and ${Si}_3N_4$/InP PECVD interface were chracterized by TEM and AES.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.3_1spc
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• pp.504-508
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• 2013

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

• Transactions of the Society of Information Storage Systems
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• v.2 no.2
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• pp.96-99
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• 2006

In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Journal of the Korean Applied Science and Technology
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• v.16 no.1
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• pp.33-40
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• 1999

We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-$H_2O_2$ and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-$H_2O_2$ solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-$H_2O_2$ solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-$H_2O_2$ solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-$H_2O_2$ solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-$H_2O_2$ solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the $NH_4OH-H_2O_2-H_2O$ and $HCl-H_2O_2-H_2O$ cleaning.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.430-430
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• 2008

Using multi plasma enhanced chemical vapor deposition system (Multi-PECVD), p-a-Si:H deposition layer as a $p^+$ region which was annealed by laser (Q-switched fiber laser, $\lambda$ = 1064 nm) on an n-type single crystalline Si (100) plane circle wafer was prepared as new doping method for single crystalline interdigitated back contact (IBC) solar cells. As lots of earlier studies implemented, most cases dealt with the excimer (excited dimer) laserannealing or crystallization of boron with the ultraviolet wavelength range and $10^{-9}$ sec pulse duration. In this study, the Q-switched fiber laser which has higher power, longer wavelength of infrared range ($\lambda$ = 1064 nm) and longer pulse duration of $10^{-8}$ sec than excimer laser was introduced for uniformly deposited p-a-Si:H layer to be annealed and to make sheet resistance expectable as an important process for IBC solar cell $p^+$ layer on a polished n-type Si circle wafer. A $525{\mu}m$ thick n-type Si semiconductor circle wafer of (100) plane which was dipped in a buffered hydrofluoric acid solution for 30 seconds was mounted on the Multi-PECVD system for p-a-Si:H deposition layer with the ratio of $SiH_4:H_2:B_2H_6$ = 30:120:30, at $200^{\circ}C$, 50 W power, 0.2 Torr pressure for 20 minutes. 15 mm $\times$ 15 mm size laser cut samples were annealed by fiber laser with different sets of power levels and frequencies. By comparing the results of lifetime measurement and sheet resistance relation, the laser condition set of 50 mm/s of mark speed, 160 kHz of period, 21 % of power level with continuous wave mode of scanner lens showed the features of small difference of lifetime and lowering sheet resistance than before the fiber laser treatment with not much surface damages. Diode level device was made to confirm these experimental results by measuring C-V, I-V characteristics. Uniform and expectable boron doped layer can play an important role to predict the efficiency during the fabricating process of IBC solar cells.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.314-314
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• 2012

The dilute magnetic semiconductors (DMS) have been developed to multi-functional electro-magnetic devices. Specially, the Si based DMS formed by ion implantation have strong advantages to improve magnetic properties because of the controllable effects of carrier concentration on ferromagnetism. In this study, we investigated the deep level states of Fe- and Co-ions implanted Si wafer during rapid thermal annealing (RTA) process. The p-type Si (100) wafers with hole concentration of $1{\times}10^{16}cm^{-3}$ were uniformly implanted by Fe and Co ions at a dose of $1{\times}10^{16}cm^{-2}$ with an energy of 60 keV. After RTA process at temperature ranges of $500{\sim}900^{\circ}C$ for 5 min in nitrogen ambient, the Au electrodes with thickness of 100 nm were deposited to fabricate a Schottky contact by thermal evaporator. The surface morphology, the crystal structure, and the defect state for Fe- and Co- ion implanted p-type Si wafers were investigated by an atomic force microscopy, a x-ray diffraction, and a deep level transient spectroscopy, respectively. Finally, we will discuss the physical relationship between the electrical properties and the variation of defect states for Fe- and Co-ions implanted Si wafer after RTA.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.322-322
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• 2010

For boron doping on n-type silicon wafer, around $1,000^{\circ}C$ doping temperature is required, because of the relatively low solubility of boron in a crystalline silicon comparing to the phosphorus case. Boron doping by fiber laser annealing and lamp furnace heat treatment were carried out for the uniformly deposited p-a-Si:H layer. Since the uniformly deposited p-a-Si:H layer by cluster is highly needed to be doped with high temperature heat treatment. Amorphous silicon layer absorption range for fiber laser did not match well to be directly annealed. To improve the annealing effect, we introduce additional lamp furnace heat treatment. For p-a-Si:H layer with the ratio of $SiH_4:B_2H_6:H_2$=30:30:120, at $200^{\circ}C$, 50 W power, 0.2 Torr for 30 min. $20\;mm\;{\times}\;20\;mm$ size fiber laser cut wafers were activated by Q-switched fiber laser (1,064 nm) with different sets of power levels and periods, and for the lamp furnace annealing, $980^{\circ}C$ for 30 min heat treatment were implemented. To make the sheet resistance expectable and uniform as important processes for the $p^+$ layer on a polished n-type silicon wafer of (100) plane, the Q-switched fiber laser used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the fiber laser treatment showed the trade-offs between the lifetime and the sheet resistance as $100\;{\omega}/sq.$ and $11.8\;{\mu}s$ vs. $17\;{\omega}/sq.$ and $8.2\;{\mu}s$. Diode level device was made to confirm the electrical properties of these experimental results by measuring C-V(-F), I-V(-T) characteristics. Uniform and expectable boron heavy doped layers by fiber laser and lamp furnace are not only basic and essential conditions for the n-type crystalline silicon solar cell fabrication processes, but also the controllable doping concentration and depth can be established according to the deposition conditions of layers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.