• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1277-1279
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• 1994

In the structure of ZnO/nip-SiC: H/metal substrate amorphous silicon (a-Si:H) solar cells, the effects of inserting a rear textured ZnO in the p-SiC:H/metal interface and a graded bandgap buffer layer in the i/p-SiC:H have been analysed by computer simulation. The incident light was taken to have an intensity of $100mW/cm^2$(AM-1). The thickness of the a-Si:H n, ${\delta}$-doped a-SiC:H p, and buffer layers was assumed to be $200{\AA},\;66{\AA}$, and $80{\AA}$, respectively. The scattering coefficients of the front and back ZnO were taken to be 0.2 and 0.7, respectively. Inserting the rear buffer layer significantly increases the open circuit voltage($V_{oc}$) due to reduction of the i/p interface recombination rate. The use of textured ZnO markedly improves collection efficiency in the long wavelengths( above ${\sim}550nm$ ) by back scattering and light confinement effects, resulting in dramatic enhancement of the short circuit current density($J_{sc}$). By using the rear buffer and textured ZnO, the i-layer thickness of the ceil for obtaining the maximum efficiency becomes thinner(${\sim}2500{\AA}$). From these results, it is concluded that the use of textured ZnO and buffer layer at the backside of the ceil is very effective for enhancing the conversion efficiency and reducing the degradation of a-Si:H pin-type solar cells.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.418.2-418.2
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• 2016

$Al_2O_3$ passivation layer has excellent passivation properties at p-type Si surface. This $Al_2O_3$ layer forms thin $SiO_2$ layer at the interface. There were some studies about inserting thermal oxidation process to replace naturally grown oxide during $Al_2O_3$ deposition. They showed improving passivation properties. However, thermal oxidation process has disadvantage of expensive equipment and difficult control of thin layer formation. Wet chemical oxidation has advantages of low cost and easy thin oxide formation. In this study, $Al_2O_3$/$SiO_2/Si(100)$ interface was formed by wet chemical oxidation and PA-ALD process. $SiO_2$ layer at Si wafer was formed by $HCl/H_2O_2$, $H_2SO_4/H_2O_2$ and $HNO_3$, respectively. 20nm $Al_2O_3$ layer on $SiO_2/Si$ was deposited by PA-ALD. This $Al_2O_3/SiO_2/Si(100)$ interface were characterized by capacitance-voltage characteristics and quasi-steady-state photoconductance decay method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.218-219
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• 2008

In this paper, we have investigated the phase change memory device with cell structure using three-dimensional finite element analysis tool for reducing reset current. From the simulation, the reset current of PRAM with $SiO_2$ inserting layer is greatly reduced, compared with the conventional device.

• Journal of Digital Convergence
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• v.12 no.7
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• pp.291-296
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• 2014

Inserting a $SiO_2$ layer underneath the p-pad electrode as the current blocking layer (CBL) structure and extending p-metal finger patterns, the GaN LEDs using an indium-tin-oxide (ITO) layer show the improved light output intensity, resulting from better current spreading and reduced light loss on the surface of p-pad metal. The LEDs with an oxide layer of $100{\mu}m$-pad-width and $6{\mu}m$-finger-width have better light output intensities than those with an oxide layer of $105{\mu}m$-pad-width and $12{\mu}m$-finger-width. Using the ATLAS device simulator from Silvaco Corporation, the current density distributions on the active layer in CBL LEDs have been investigated.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.958-961
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• 2007

The electrical characteristics of organic thin-filmtransistor (OTFTs) can be improved by inserting adhesion layer on gate dielectrics. Adhesion layer was used as polymeric adhesion layer deposited on inorganic gate insulators such as silicon dioxide $(SiO_2)$ and it was formed by vapor deposition polymerization (VDP) instead of spin-coating process. The OTFTs obtained the on/off ratio $of{\sim}10^4$, threshold voltage of 1.8V, subthreshold slop of 2.9 V/decade and field effect mobility about $0.01\;cm^2/Vs$.

• Korean Journal of Materials Research
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• v.21 no.6
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• pp.341-346
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• 2011

In this study, we inserted a Zn buffer layer into a AZO/p-type a-si:H layer interface in order to lower the contact resistance of the interface. For the Zn layer, the deposition was conducted at 5 nm, 7 nm and 10 nm using the rf-magnetron sputtering method. The results were compared to that of the AZO film to discuss the possibility of the Zn layer being used as a transparent conductive oxide thin film for application in the silicon heterojunction solar cell. We used the rf-magnetron sputtering method to fabricate Al 2 wt.% of Al-doped ZnO (AZO) film as a transparent conductive oxide (TCO). We analyzed the electro-optical properties of the ZnO as well as the interface properties of the AZO/p-type a-Si:H layer. After inserting a buffer layer into the AZO/p-type a-Si:H layers to enhance the interface properties, we measured the contact resistance of the layers using a CTLM (circular transmission line model) pattern, the depth profile of the layers using AES (auger electron spectroscopy), and the changes in the properties of the AZO thin film through heat treatment. We investigated the effects of the interface properties of the AZO/p-type a-Si:H layer on the characteristics of silicon heterojunction solar cells and the way to improve the interface properties. When depositing AZO thin film on a-Si layer, oxygen atoms are diffused from the AZO thin film towards the a-Si layer. Thus, the characteristics of the solar cells deteriorate due to the created oxide film. While a diffusion of Zn occurs toward the a-Si in the case of AZO used as TCO, the diffusion of In occurs toward a-Si in the case of ITO used as TCO.

• Journal of the Korean Ceramic Society
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• v.39 no.4
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• pp.377-385
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• 2002

The possibility of $ZrO_2$ thin film as insulator for Metal-Ferroelectric-Insulator-Semiconductor(MFIS) structure was investgated. $SrBi_2Ta_2O_9$ and $SrBi_2Ta_2O_9$(SBT) thin films were deposited on P-type Si(111) wafer by R. F. magnetron sputtering method. The electrical properties of MFIS gate were relatively improved by inserting the $ZrO_2$ buffer layer. The window memory increased from 0.5 to 2.2V in the applied gate voltage range of 3-9V when the thickness of SBT film increased from 160 to 220nm with 20nm thick $ZrO_2$. The maximum value of window memory is 2.2V in Pt/SBT(160nm)/$ZrO_2$(20nm)/Si structure with the optimum thickness of $ZrO_2$. These memory windows are sufficient for practical application of NDRO-FRAM operating at low voltage.

• Journal of the Korean Ceramic Society
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• v.35 no.10
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• pp.1107-1112
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• 1998

We could obtan c-axis oriented $SrBi_2$$Ta_2$$O_9$ thin films on usual Pt(111)/Ti/$SiO_2$/Si(100) substrate using a r. f. magnetron sputtering technique. According to the increase of sputtering pressure from 250 to 300 mTorr the Bi content and degree of the c-a xis preferred orientation of $SrBi_2$$Ta_2$$O_9$ thin films were increased. By controlling Bi(or $Bi_2O_3$) loss from $SrBi_2$$Ta_2$$O_9$ thin films during post annealing and by inserting $Bi_2O_3$ layer in $SrBi_2$$Ta_2$$O_9$ thin films the effect of Bi content on the c-axis oriented growth of $SrBi_2$$Ta_2$$O_9$ thin films could be investigated without the effect of sputtering pressure. The degree of the c-axis preferred orientation of $SrBi_2$$Ta_2$$O_9$ thin films was increased with increasing with increasing Bi content by control of Bi(or $Bi_2O_3$) loss of $SrBi_2$$Ta_2$$O_9$ thin films. But the c-axis oriented growth of $SrBi_2$$Ta_2$$O_9$ thin films disappeared by the inserting of $Bi_2O_3$ lay-er in $SrBi_2$$Ta_2$$O_9$ thin films.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.1-7
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• 2004

In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.

• Journal of the Korean Magnetics Society
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• v.16 no.6
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• pp.279-282
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• 2006

Magnetic tunnel junctions (MTJs), which consisted of amorphous ferromagnetic NiFeSiB free layers, were investigated. The NiFeSiB layers were used to substitute for the traditionally used CoFe and/or NiFe layers with the emphasis being given to obtaining an understanding of the effect of the amorphous free layer on the switching characteristics of the MTJs. $Ni_{16}Fe_{62}Si_{8}B_{14}$ has a lower saturation magnetization ($M_{s}:\;800\;emu/cm^{3}$) than $Co_{90}Fe_{10}$ and a higher anisotropy constant ($K_{u}:\;2700\;erg/cm^{3}$) than $Ni_{80}Fe_{20}$. The $Si/SiO_{2}/Ta$ 45/Ru 9.5/IrMn 10/CoFe $7/AlO_{x}/CoFeSiB\;(t)/Ru\;60\;(in\;nanometers)$structure was found to be beneficial for the switching characteristics of the MTJ, leading to a reduction in the coercivity ($H_{c}$) and an increase in the sensitivity resulted from its lower saturation magnetization and higher uniaxial anisotropy. Furthermore, by inserting a very thin CoFe layer at the tunnel barrier/NiFeSiB interface, the TMR ratio and switching squareness were improved more with the increase of NiFeSiB layer thickness up to 11 nm.