• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.449-452
• /
• 1998

We have studied the oxidatio nrte of $Si_{1-x}Ge_{x}$ epitaxial layer grown by MBE(molecular beam epitaxy). Oxidation were performed at 700.deg. C, 800.deg. C, 900.deg. C, and 1000.deg. C. After the oxidation, the results of AES(auger electron spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $SiO_{2}/$Si_{1-x}Ge_{x}$ interface. It is shown that the presence of Ge at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700.deg. C and 800.deg.C, while it was decreased at both 900.deg. C and 1000.deg.C as the Ge mole fraction was increased. The ry oxidation rates were reduced for heavy Ge concentration, and large oxidation time. In the parabolic growth region of $Si_{1-x}Ge_{x}$ oxidation, The parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the 1000.deg.C, AES showed that Ge peak distribution at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface reduced by interdiffusion of silicon and germanium.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.12
• /
• pp.1080-1086
• /
• 2005

We have studied the Ge redistribution after dry oxidation and the oxide growth rate of $Si_{1-x}Ge_x$ epitaxial layer. Oxidation were performed at 700, 800, 900, and $1,000\;^{\circ}C$. After the oxidation, the results of RBS (Rutherford Back Scattering) & AES(Auger Electron Spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $Si_{1-x}Ge_x$ interface. It is shown that the presence of Ge at the $Si_{1-x}Ge_x$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700 and 800$^{\circ}C$, while it was decreased at both 900 and $1,000^{\circ}C$ as the Ge mole fraction was increased. The dry of idation rates were reduced for heavy Ge concentration, and large oxiidation time. In the parabolic growth region of $Si_{1-x}Ge_x$ oxidation, the parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the $1,000^{\circ}C$, AES showed that Ge peak distribution at the $Si_{1-x}Ge_x$ interface reduced by interdiffusion of silicon and germanium.

• Electrical & Electronic Materials
• /
• v.8 no.1
• /
• pp.71-76
• /
• 1995

The thermal oxidation of Ge$_{0.2}$Si$_{0.8}$ in wet ambient has been investigated by Rutherford Backscattering Spectrometry(RBS). A uniform Ge$_{0.2}$Si$_{0.8}$O$_{2}$ oxide is formed at temperatures below 650.deg. C for polycrystalline and below 700.deg. C for single crystalline substrates. At higher temperatures Ge becomes depleted from the oxide and finally SiO$_{2}$ oxide is formed with Ge piled-ub behind it. The transition between the different oxide types depends also on the crystallinity of Ge$_{0.2}$Si$_{0.8}$. When a uniform Ge$_{0.2}$Si$_{0}$8/O$_{2}$ oxide grows, its thickness is proportional to the square root of the oxidation time, which suggests that the rate noting process is the diffusive transport of oxidant across the oxide. It is believed the oxidation is controlled by the competition between the diffusion of Ge or Si in Ge$_{0.2}$Si$_{0.8}$ and the movement of oxidation front.t.oxidation front.t.

• Journal of the Korean Vacuum Society
• /
• v.9 no.4
• /
• pp.346-352
• /
• 2000

We investigated the oxidation behavior of poly $Si_{1-x}Ge_x$ films (X=0.15, 0.42) at $700^{\circ}C$ in wet oxidation ambients and analyzed the oxide by XPS, RBS, and cross-sectional TEM. In the case of poly $Si_{0.85}Ge_{0.15}$ films, $SiO_2$ was formed on the poly $Si_{1-x}Ge_x$ films and Ge was rejected from growing oxide, subsequently leading to the increase of Ge content. In the case of poly $Si_{0.58}Ge_{0.42}$ films, we found that $SiO_2-GeO_2$ were formed on the poly $Si_{1-x}Ge_x$ films due to high Ge content. Finally, we proposed the oxidation model of poly $Si_{1-x}Ge_x$ films.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.9
• /
• pp.765-770
• /
• 2003

We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.143.1-143.1
• /
• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• Journal of the Korean Vacuum Society
• /
• v.8 no.2
• /
• pp.148-152
• /
• 1999

the low temperature magnetoresistance effect, electron mobilities, and 2 Dimensional electron Gases (2DEG) properties were investigated in $Si/Si_{1-x}Ge_x$ quantum well devices. N-type $Si/Si_{1-x}Ge_x$ structures were fabricated by utilizing a gas source Molecular Beam Epitaxy (GSMBE). Thermal oxidation was carried out in a dry O atmosphere at $700^{\circ}C$ for 7 hours. Electron mobilities were measured by using a Hall effect and a magnetoresistant effect at low temperatures down to 0.4K. Pronounced Shubnikov-de Haas (SdH) oscillations were observed at a low temperature showing two dimensional electron gases (2DEG) in s tensile strained Si quantum well. The electron sheet density (ns) of $1.5\times10^{12}[\textrm{cm}^{-2}]$ and corresponding electron mobility of 14200 $[\textrm{cm}^2V^{-1}s^{-1}]$ were obtained at a low temperature of 0.4K from $Si/Si_{1-x}Ge_x$ structures with thermally grown oxides.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.453-456
• /
• 1998

The electrical properties of $Si_{1-x}Ge_{x}$ samples have been investigated. The sample structures were grown by MBE (molecular geam epitaxy) with Ge mole-fraction of x=0.0, x=0.05, x=0.1, and x=0.2. To examine the influence of the thermal processing, the $O_{2}$ and N$_{2}$ process were performed at 800[.deg. C] and 900[.deg. C], respectively. After this thermal process, hall measurements have been done over a wide range of the ambient temperature between 320[.deg. K] and 10[.deg. K] to find the temperature dependence using the comparessed-He gas system. The Ge-rich layer has been formed at the $SiO_{2}$/SiGe interface and it has an effect on the hall mobility. And it has been found that hall mobility was increased by the $N_{2}$ annealing process comparing with dry oxidation process at both 800[.deg.C] and900[.deg. C].

• Journal of Korean Vacuum Science & Technology
• /
• v.4 no.1
• /
• pp.11-17
• /
• 2000

The low temperature electron mobilities were investigated in Si/$Si_{1-x}Ge_{x}$ modulation Doped (MOD) quantum well structure with thermally grown oxide. N-type Si/$Si_{1-x}Ge_{x}$ structures were fabricated by a gas source MBE. Thermal oxidation was carried out in a dry $O_2$ atmosphere at $700^{\circ}C$ for 7 hours. Electron mobilities were measured by a Hall effect and a magnetoresistant effect at low temperatures down to 0.4 K. Pronounced Shubnikov-de Haas (SdH) oscillations were observed at a low temperature showing two dimensional electron gases (2 DEG) in a tensile strained Si quantum well. The electron sheet density ($n_{s}$) of 1.5${\times}$$10^{12}$[$cm^{-2}$] and corresponding electron mobility of 14200 [$cm^2$$V^{-1}$$s^{-1}$] were obtained at low temperature of 0.4 K from Si/$Si_{1-x}Ge_{x}$ MOD quantum well structure with thermally grown oxide.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.08a
• /
• pp.155.2-155.2
• /
• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.