• 대한전자공학회논문지
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• 제26권11호
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• 한국정보통신학회논문지
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• 제4권3호
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• pp.713-719
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• 2000

고체상 켜쌓기법(solid phase epitaxy)으로$Ge_xSi_{1-x}/Si$(111) 이종접합을 형성하기 위해 Si(111) 기판위에 먼저 Au를 1000A 증착하고 그 위에 Ge을 1000A 증착시켜 a-Ge/Au/Si(111)구조를 형성하고 이를 고진공 조건에서 이단계 열처리 하였다. 열처리 후 Auger 전자분광분석(AES), X-ray 회절(XRD), 고분해 투과전자현미경(HRTEM) 등을 통해 Au와 Ge의 거동과 형성된 $Ge_xSi_{1-x}$막의 특성을 열처리 조건에 따라 분석하였다. a-Ge/Au/Si(111)구조는 열처리에 의해 Au/GeSi/Si(111)의 구조로 변했으며 형성된$Ge_xSi_{1-x}/$((111)층은 Si(111) 기판의 면 방향과 잘 일치하였다. 그러나 $Ge_xSi_{1-x}/Si$((111)층 내부에 적층결함, 전이, 쌍정, planar defect 등이 주로 (111)면 방향으로 형성되어 있음을 알 수 있었다.

• 전자공학회논문지A
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• 제32A권2호
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1996년도 재료학회 춘계학술발표회
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• pp.30-30
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• 1996

• 한국재료학회:학술대회논문집
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• 한국재료학회 1994년도 춘계 학술발표 강연 및 논문 개요집
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• pp.127-127
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• 1994

• 한국재료학회:학술대회논문집
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• 한국재료학회 1994년도 춘계 학술발표 강연 및 논문 개요집
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• pp.128-129
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• 1994

• 한국재료학회지
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• 제4권8호
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• pp.895-905
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• 1994

비정질 $Si_{1-x}Ge_{x}$(X=0, 0.14, 0.34, 0.53)합금박막의 결정화거동을 X-ray diffractometry(XRD)와 투과전자현미경(transmission electron microscopy, TEM)을 이용하여 조사하였다. 비정질 박막은 열산화막(thermal oxide, $SiO_{2}$)이 입혀진 Si기판위에 MBE(Molecular Beam Epitaxy)를 이용하여 $300^{\circ}C$에서 증착하였으며 각 Ge조성에 해당하는 기편들을 $500^{\circ}C$ ~ $625^{\circ}C$에서 열처리한 다음 XRD를 이용하여 결정화분율과 결정화후 박막의 우선순방위(texture)경향ㅇ르 조사하였다. 또한 TEM을 사용하여 열처리한 박막의 미세구조를 분석하였다. XRD분석결과 박막내의 Ge함량의 증가는 결정화에 대한 열처리시간을 크게 감소시키는 것으로 밝혀졌다. 또한 결정화후 강한(111) 우선방위를 나타내는 Si박막과는 달리 $Si_{1-x}Ge_{x}$합금은 (311)우선방위를 가지는 것을 알았으며 이는 비정질 Si박막과 $Si_{1-x}Ge_{x}$박막의 결정화기구에 현저한 차이가 있음을 암시한다. TEM관찰에서, 순수한 Si박막은 결정화후 결정립이 타원형이나 수지상(dendrite)형태를 취하고 있었으며 결정립내부에 미페쌍정이나 적층결함들의 많은 결정결함들이 존재하고, 결정립의 성장이 이들 결함을 따라 우선적으로 성장함을 알 수 있었다. 반면에 $Si_{0.47}Ge_{0.53}$의 경우에서는 결정립모양이 원형에 가까운 동축정(dquiaxed)형상을 하며 결정립내부의 결함밀도도 매우 낮았다. 특히 Si에서 보았던 결정립성장의 방향성은 관찰되지 않았다. 이상의 결과에서 비정질 $Si_{1-x}Ge_{x}$(합금박막의 결정화는 Ge이 포함되지 않은 순수한 Si의 twin assisted growth mode에서 Ge 함량의 증가에 따라 \ulcorner향성이 없는 random growth mode로 전개되어간다고 결론지을수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.449-452
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• 1998

We have studied the oxidatio nrte of $Si_{1-x}Ge_{x}$ epitaxial layer grown by MBE(molecular beam epitaxy). Oxidation were performed at 700.deg. C, 800.deg. C, 900.deg. C, and 1000.deg. C. After the oxidation, the results of AES(auger electron spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $SiO_{2}/$Si_{1-x}Ge_{x}$ interface. It is shown that the presence of Ge at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700.deg. C and 800.deg.C, while it was decreased at both 900.deg. C and 1000.deg.C as the Ge mole fraction was increased. The ry oxidation rates were reduced for heavy Ge concentration, and large oxidation time. In the parabolic growth region of $Si_{1-x}Ge_{x}$ oxidation, The parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the 1000.deg.C, AES showed that Ge peak distribution at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface reduced by interdiffusion of silicon and germanium.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• 한국진공학회지
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• 제8권2호
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• pp.148-152
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• 1999

the low temperature magnetoresistance effect, electron mobilities, and 2 Dimensional electron Gases (2DEG) properties were investigated in $Si/Si_{1-x}Ge_x$ quantum well devices. N-type $Si/Si_{1-x}Ge_x$ structures were fabricated by utilizing a gas source Molecular Beam Epitaxy (GSMBE). Thermal oxidation was carried out in a dry O atmosphere at $700^{\circ}C$ for 7 hours. Electron mobilities were measured by using a Hall effect and a magnetoresistant effect at low temperatures down to 0.4K. Pronounced Shubnikov-de Haas (SdH) oscillations were observed at a low temperature showing two dimensional electron gases (2DEG) in s tensile strained Si quantum well. The electron sheet density (ns) of $1.5\times10^{12}[\textrm{cm}^{-2}]$ and corresponding electron mobility of 14200 $[\textrm{cm}^2V^{-1}s^{-1}]$ were obtained at a low temperature of 0.4K from $Si/Si_{1-x}Ge_x$ structures with thermally grown oxides.