• Electrical & Electronic Materials
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• v.12 no.8
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• pp.24-29
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• 1999

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.213-216
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• 2004

This paper describes design and implementation of the 5.5 GHz VCO with parallel-branch inductors using 0.8${\mu}m$ SiGe HBT process technology. The proposed parallel-branch inductor shows $12 \%$ improvement in quality factor in comparison with the conventional inductor. A phase noise of -93 dBc/Hz is measured at 100 kHz offset frequency, and the harmonics in the VCO are suppressed less than -23 dBc. The single-sided output power of the VCO is -6.5$\pm$1.5 dBm. The manufactured VCO consumes 15.0 mA with 2.5 V supply voltage. Its chip areas are 1.8mm ${\times}$ 1.2mm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.439-445
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• 2007

SiGe integrated circuits are being used in the field of high-speed wire/wireless communications and microwave systems due to the RF/high-speed analog characteristics and the easiness in the fabrication. Reducing the resistance variation in SiGe thin film resistors results in enhancing the reliability of integrated circuits. In this paper, we investigate the causes that generate the resistance nonuniformity after the silicon-based thin film resistor was fabricated, and consider the counter plan against that. Because the Ti-B precipitate, which formed during the silicide process of the SiGe thin film resistor, gives rise to the nonuniformity of SiGe resistors, the boron ions should be implanted as many as possible. In addition, the resistance deviation increases as the size of the contact hole that interconnects the SiGe resistor and the metal line decreases. Therefore, the size of the contact hole must be enlarged in order to reduce the resistance deviation.

• ETRI Journal
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• v.15 no.3
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• pp.61-69
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• 1994

A new analytical model for the base current of Si/SiGe/Si heterojunction bipolar transistors(HBTs) has been developed. This model includes the hole injection current from the base to the emitter, and the recombination components in the space charge region(SCR) and the neutral base. Distinctly different from other models, this model includes the following effects on each base current component by using the boundary condition of the excess minority carrier concentration at SCR boundaries: the first is the effect of the parasitic potential barrier which is formed at the Si/SiGe collector-base heterojunction due to the dopant outdiffusion from the SiGe base to the adjacent Si collector, and the second is the Ge composition grading effect. The effectiveness of this model is confirmed by comparing the calculated result with the measured plot of the base current vs. the collector-base bias voltage for the ungraded HBT. The decreasing base current with the increasing the collector-base reverse bias voltage is successfully explained by this model without assuming the short-lifetime region close to the SiGe/Si collector-base junction, where a complete absence of dislocations is confirmed by transmission electron microscopy (TEM)[1].The recombination component in the neutral base region is shown to dominate other components even for HBTs with a thin base, due to the increased carrier storage in the vicinity of the parasitic potential barrier at collector-base heterojunction.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2064-2066
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• 2004

본 논문에서는 새로운 개념인 능동 고조파 결합을 이용한 4위상 전압제어 발진기를 설계, 제작하였다. 4위상 출력 특성을 얻기 위하여 각각의 차동 VCO의 가상 접지(Virtual Ground)면을 본 논문에 제시된 능동 고조파 결합 회로(Active super harmonic coupling)을 이용하여 결합시키는 방법을 적용하였다. 제안된 구조는 다음과 같은 장점을 가지고 있다. 결합구조를 갖는 트랜지스터에 부가적인 전류소비를 줄일 수 있으며, layout상에서 문제되었던 대칭구조를 개선할 수 있다. 또한 기존에 발표되었던 방법인 passive transformer를 이용한 고조파 결합 보다 회로 크기를 줄일 수 있다. 측정결과 출력 전력 -12dBm, -117dBc/Hz @1-MHz 이하의 위상잡음 특성, 2.66GHz${\sim}$2.91GHz의 250 MHz 주파수 가변, 25dB이하의 2차고조파 억압, 7 mA 의 전류 소모(buffer amp. 포함되지 않음)를 가졌다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.179-182
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• 2002

In this paper, 2-stage Power amplifier with external bias controller for\ulcorner IMT-2000 handsets was designed using SiGe HBT with excellent linearity to 1\ulcornereduce size and weight. The designed amplifier has 26.5 dBm output power, 33% power added efficiency, and 22 dB linear power gain in 1920-1980MHz frequency range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.182-185
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• 2002

자기정렬구조의 실리콘-게르마늄 이종접합 트랜지스터에서 $f_{max}$를 높이기 위한 방안으로 베이스의 저항 값을 감소시키고자 외부 베이스에 실리콘 및 실리콘-게르마늄 박막을 저온에서 선택적으로 성장할 수 있는 방법을 연구하였다. RPCVD를 이용하여 $SiH_{2}Cl_{2}$과 $GeH_{4}$를 소스 가스로 하고 HCI을 첨가하여 선택성을 향상시킴으로써 $675\sim725^{\circ}C$의 저온에서도 실리콘 및 실리콘-게르마늄의 선택적 에피성장이 가능하였다. 고온 공정에 주로 이용되는 $SiH_{2}Cl_{2}$를 이용한 실리콘 증착은 $675^{\circ}C$에서 열분해가 잘 이루어지지 않고 HCl의 첨가에 의한 식각반응이 동시에 진행되어 실리콘 기판에서도 증착이 진행되지 않으나 $700^{\circ}C$ 이상에서는 HCI을 첨가한 경우에 한해서 선택성이 유지되면서 실리콘의 성장이 이루어졌다, 반면 실리콘-게르마늄막은 실리콘에 비해 열분해 온도가 낮고 GeO를 형성하여 잠입시간을 지연하는 효과가 있는 게르마늄의 특성으로 인해 선택성이나 증착속도 모두에서 유리하였으나 실리사이드 공정시에 표면으로 게르마늄이 석출되는 현상 등의 저항성분이 크게 작용하여 실리콘-게르마늄막 만으로는 외부 베이스에의 적용은 적절하지 않았다. 그러나 실리콘막을 실리콘-게르마늄막 위에 Cap 층으로 증착하거나 실리콘막 만으로 외부 베이스에 선택적으로 증착하여 베이스의 저항을 70% 가량 감소시킬 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.276-279
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• 2015

This paper presents two 3-stage D-band stacked amplifiers developed in a $0.13-{\mu}m$ SiGe BiCMOS technology, employed to compare the conventional cascode topology and the common-base (CB)/CB stacked topology. AMP1 employs two cascode stages followed by a CB/CB stacked stage, while AMP2 is composed of three CB/CB stacked stages. AMP1 showed a 17.1 dB peak gain at 143.8 GHz and a saturation output power of -4.2 dBm, while AMP2 showed a 20.4 dB peak gain at 150.6 GHz and a saturation output power of -1.3 dBm. The respective power dissipation was 42.9 mW and 59.4 mW for the two amplifiers. The results show that CB/CB stacked topology is favored over cascode topology in terms of gain near 140 GHz.