• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.70-70
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• 2003

금속용액을 이용하여 측면고상결정화 시킨 다결정 실리콘 박막내의 고각입계를 줄이기 위해 서 고온열처리를 실시하였다. SEM과 TEM을 이용하여 다결정 실리콘내의 바늘모양의 결정립의 폭의 증가를 관찰하였고, 결정 립내의 결함이 감소를 관찰하였다. 그리고 결정화된 다결정 실리콘의 표면 거칠기를 AFM이용하여 퍼니스에서 53$0^{\circ}C$에서 25시간 동안 결정화 시킨 시편과 이후 80$0^{\circ}C$에서 40분간 추가 고온 열처리시킨 시편을 비교한 결과 6.09$\AA$에서 4.22$\AA$으로 개선되었음을 확인할 수 있었다. 박막내의 금속에 의한 오염을 줄이기 위해 금속의 농도를 줄인 금속용액을 결정화에 사용하였다. 이때 저농도 금속용액을 사용하여 측면결정화시킨 다결정 실리콘 박막내의 소각입계를 이루는 결정립군의 크기가 고농도 금속용액을 이용하여 측면결정화시킨 경우보다 증가함을 확인 할 수 있었다. 박막트랜지스터를 제작하여 트랜지스터의 전기적특성을 살펴보았다. 전계이동도가 80$0^{\circ}C$ 고온 열처리에 의해서 53$\textrm{cm}^2$/Vsec 에서 95$\textrm{cm}^2$/Vsec 로 상승하였는데 이는 고온열처리에 의해서 측면결정화된 다결정 실리콘내의 트랩 밀도가 2.2$\times$$10^{12}$/$\textrm{cm}^2$ 에서 1.3$\times$$10^{12}$$\textrm{cm}^2$로 감소하였기 때문이다.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1645-1647
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• 1996

Polycrystalline CdTe thin films -have been studied for photovoltaic application because of their high absorption coefficient and optimal band gap energy (1.54 eV) for solar energy conversion. In this study, we prepared CdTe films using RF-magnetron sputtering method and investigated structural, optical and electrical properties with spectrophotometer, XRD, EDX, and resistivity meter. CdTe films at $200\;^{\circ}C$ showed a mixture of zinc blend (Cubic) and wurtzite (hexagonal) phase. On the other hand, the films at $400\;^{\circ}C$ showed highly oriented structure having hexagonal structure. The resistivity of CdTe films deposited on $SiO_2$ substrates was about $10_7\;{\Omega}cm$. The value of resistivity decreased with the increase of the substrate temperature. CdTe were sputtered on CdS thin films prepared by chemical bath deposition for the formation of the heterojunction. I-V characteristics of these cells were measured at a light density of $100mw/cm^2$, AM. 1.0. The present thin film solar cells showed a conversion efficiency of about 5%.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.253-256
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• 2017

A thin Te interlayer was applied to a Ni/n-InGaAs contact to reduce the contact resistance between Ni-InGaAs and n-InGaAs. A 5-nm-thick Te layer was first deposited on a Si-doped n-type $In_{0.53}Ga_{0.47}As$ layer, followed by in situ deposition of a 30-nm-thick Ni film. After the formation of the Ni-InGaAs alloy by rapid thermal annealing at $300^{\circ}C$ for 30 s, the extracted specific contact resistivity (${\rho}_c$) reduced by more than one order of magnitude from $2.86{\times}10^{-4}{\Omega}{\cdot}cm^2$ to $8.98{\times}10^{-6}{\Omega}{\cdot}cm^2$ than that of the reference sample. A thinner Ni-InGaAs alloy layer with a better morphology was obtained by the introduction of the Te layer. The improved interface morphology and the graded Ni-InGaAs layer formed at the interface were believed to be responsible for ${\rho}_c$ reduction.

• Journal of the Korean Magnetic Resonance Society
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• v.12 no.1
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• pp.26-32
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• 2008

We report on the ferromagnetic characteristics of $Zn_{1-x}Mn_xO$ films (x = 0.3) prepared by sol-gel method on the silicon and (0001) ${\alpha}-Al_2O_3$ substrates at the annealing temperature of 700$^{\circ}C$. Magnetic measurements show that Curie temperature ($T_C$) and the coercive field ($H_C$) for the film on the silicon are about 32 K and about 275 Oe, while those for that on the sapphire are about 32 K and 425 Oe, respectively. Energy dispersive spectroscopy and transmission electron microscopy measurements suggest that ferromagnetic precipitates originated by manganese oxide compound formed at the interfaces of the both substrates may be responsible for the observed ferromagnetic behavior of the films. Electron paramagnetic resonance study of the powders up to the concentration of x=0.15 supports the result.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.44-44
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• 2003

Growth mechanism of carbon nanotubes(CNTs) synthesized by chemical vapor deposition is abided by two growth modes. These growth modes are classified by the position of activated catalytic metal particle in the CNTs. Growth mode can be also affected by interaction between substrate and catalytic metal and induced energy such as thermal and plasma. We studied the reaction of catalytic metal to the substrate and growth mode of CNTs. Various substrates such as Si(100), graphite plate, coming glass, sapphire and AAO membrane are used to study the relation between catalytic metal and substrate in the synthesis of CNTs. For catalytic metal, thin film was deposited on various substrate via sputtering technique with a thickness of ∼20nm and magnetic fluids with none-sized particles were dispersed on AAO membrane. After laying process on AAO membrane, it was dried at 80$^{\circ}C$ for 8 hour. Synthesizing of CNTs was carried out at 900$^{\circ}C$ in NH3/C2H2 mixture gases flow for 10minutes.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.456-456
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• 2010

CMOS 소자가 서브마이크론($0.1\;{\mu}m$) 이하로 스케일다운 되면서 단채널 효과(short channel effect), 게이트 산화막(gate oxide)의 누설전류(leakage current)의 증가와 높은 직렬저항(series resistance) 등의 문제가 발생한다. CMOS 소자의 구동전류(drive current)를 높이고, 단채널 효과를 줄이기 위한 가장 효율적인 방법은 소스 및 드레인의 얕은 접합(shallow junction) 형성과 직렬 저항을 줄이는 것이다. 플라즈마 도핑 방법은 플라즈마 밀도 컨트롤, 주입 바이어스 전압 조절 등을 통해 저 에너지 이온주입법보다 기판 손상 및 표면 결함의 생성을 억제하면서 고농도로 얕은 접합을 형성할 수 있다. 그리고 얕은 접합을 형성하기 위해 주입된 불순물의 활성화와 확산을 위해 후속 열처리 공정은 높은 온도에서 짧은 시간 열처리하여 불순물 물질의 활성화를 높여주면서 열처리로 인한 접합 깊이를 얕게 해야 한다. 그러나 접합의 깊이가 줄어듦에 따라서 소스 및 드레인의 표면 저항(sheet resistance)과 접촉저항(contact resistance)이 급격하게 증가하는 문제점이 있다. 이러한 표면저항과 접촉저항을 줄이기 위한 방안으로 실리사이드 박막(silicide thin film)을 형성하는 방법이 사용되고 있다. 본 논문에서는 (100) p-type 웨이퍼 He(90 %) 가스로 희석된 $PH_3$(10 %) 가스를 사용하여 플라즈마 도핑을 실시하였다. 10 mTorr의 압력에서 200 W RF 파워를 인가하여 플라즈마를 생성하였고 도핑은 바이어스 전압 -1 kV에서 60 초 동안 실시하였다. 얕은 접합을 형성하기 위한 불순물의 활성화는 ArF(193 nm) excimer laser를 통해 $460\;mJ/cm^2$의 에니지로 열처리를 실시하였다. 그리고 낮은 접촉비저항과 표면저항을 얻기 위해 metal sputter를 통해 TiN/Ti를 $800/400\;{\AA}$ 증착하고 metal RTP를 사용하여 실리사이드 형성 온도를 $650{\sim}800^{\circ}C$까지 60 초 동안 열처리를 실시하여 $TiSi_2$ 박막을 형성하였다. 그리고 $TiSi_2$의 두께를 측정하기 위해 TEM(Transmission Electron Microscopy)을 측정하였다. 화학적 결합상태를 분석하기 위해 XPS(X-ray photoelectronic)와 XRD(X-ray diffraction)를 측정하였다. 접촉비저항, 접촉저항과 표면저항을 분석하기 위해 TLM(Transfer Length Method) 패턴을 제작하여 I-V 특성을 측정하였다. TEM 측정결과 $TiSi_2$의 두께는 약 $580{\AA}$ 정도이고 morphology는 안정적이고 실리사이드 집괴 현상은 발견되지 않았다. XPS와 XRD 분석결과 실리사이드 형성 온도가 $700^{\circ}C$에서 C54 형태의 $TiSi_2$ 박막이 형성되었고 가장 낮은 접촉비저항과 접촉저항 값을 가진다.

• Journal of the Korean Ceramic Society
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• v.33 no.5
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• pp.572-582
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• 1996

The porous silicon was prepared in the condition of 70mA/cm2 and 5.10 sec and then oxidized at 800~110$0^{\circ}C$ MOS(Metal Oxide Semiconductor) structure was prepared by Al electrode deposition and analyzed by C-V (Capacitance-Voltage) characteristics. Dielectric constant of oxidized porous silicon was large in the case of low temperature (800, 90$0^{\circ}C$) and short time(20-30min) oxidation and was nearly the same as thermal SiO2 3.9 in the case of high temperature (110$0^{\circ}C$) and long time (above 60 min) It is though to be caused byunoxidized silicon in oxidized porous silicon film and capacitance increase due to surface area increment effect.

• Journal of the Korean Ceramic Society
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• v.39 no.12
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• pp.1128-1132
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• 2002

$ReMnO_3$(Re:Y, Ho, Er) thin films were prepared by MOCVD method available to non-volatile memory device with MFS-FET structure. $ReMnO_3$ thin films were deposited on the Si(100) substrate at 700${\circ}C$ for 2h. When the films were post-annealed at 900${\circ}C$ for 1h in air, the single phase of hexagonal $ReMnO_3$ thin films were detected. Ferroelectric properties of $ReMnO_3$ thin films were dependent on the degree of c-axis orientation in the single phase of hexagonal structure and remnant polarization (Pr) of $YMnO_3$ thin films with high degree of c-axis orientation was 105 nC/$cm^2$. Leakage current density was dependent on the grain size of microstructure and that of $YMnO_3$ thin films with grain size of 100∼150 nm was $10^{-8}$ A/$cm^2$ at applied voltage of 0.5 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.218-219
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• 2009

$TiO_2$ thin films were deposited on si wafer and glass substrates by rf magnetron sputtering. The films were coated under argon atmosphere at different working pressures: 3mTorr, 5mTorr, 7mTorr, 10mTorr. The films were annealed at $550^{\circ}C$ for 5h after deposition. Film structures were analyzed with XRD, As the increase of working pressure, $TiO_2$ films have been good crystallinity. At 3mTorr and 5mTorr, the films were observed in rutile phase and anatase phase.