• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.584-592
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• 2003

6H-SiC MOSFETs and digital ICs have been fabricated and characterized. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells. NMOS and PMOS devices use a thermally grown gate oxide. SiC MOSFETs are fabricated using different impurity activation methods such as high temperature and newly proposed laser annealing methods. Several digital circuits, such as resistive road NMOS inverters, CMOS inverters, resistive road NMOS NANDs and NORs are fabricated and characterized.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.396-399
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• 2003

4H-SiC un diodes with field limiting rings(FLRs) were fabricated and characterized. The dependences of reverse breakdown voltage on the number of FLRs, the distance between p-base main junction and first FLR, and activation temperatures, were investigated. Al and B ions were implanted and activated at high temperature to form p-base region and p+ region in the n-epilayer. We have obtained up to 1782V of reverse breakdown voltage in the un diode with two FLRs on loom thick epilayer. The differential on-resistances of the fabricated diode are $5.3m{\Omega}cm^2$ at $100A/cm^2$ and $2.7m{\Omega}cm^2$ at $1kA/cm^2$, respectively. All pn diodes with FLRs have higher avalanche breakdown voltages than that of diode without an FLR. Regardless of the activation temperature, the un diode with a FLR located 5um apart from main junction has the highest mean breakdown voltage around 1600V among the diodes with one ring. On the other hand, the pn diode with two rings showed different behavior with activation temperature. It reveals that high voltage SiC pn diodes with low on-resistance can be fabricated by using the FLR edge termination.

• Korean Journal of Materials Research
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• v.11 no.7
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• pp.575-579
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• 2001

GaN buffer layer and epilayer have been grown on sapphire (0001) by metal organic chemical vapor deposition (MOCVD). GaN buffer layer ranging from 26 nm to 130 nm in thickness was grown at 55$0^{\circ}C$ prior to the 4 $\mu\textrm{m}$ thick GaN epitaxial deposition at 110$0^{\circ}C$. After GaN buffer layer growth, buffer layer surface was examined by atomic force microscopy (AFM). As the thickness of GaN buffer layer was increased, surface morphology of GaN epilayer was investigated by scanning electron microscopy (SEM). Double crystal X-ray diffraction (DCXRD) and Raman spectroscopy were employed to study crystallinity of GaN epilayers. Optical properties of GaN epilayers were measured by photoluminescence (PL). The epilayer grown with a thin buffer layer had rough surface, and the epilayer grown with a thick buffer layer had mirror-like surface of epilayer. Although the stress on the latter was larger than on the former, its crystallinity was much better. These results imply that the internal free energy is decreased in case of the thick buffer layer. Decrease in internal free energy promotes the lateral growth of the GaN film, which results in the smoother surface and better crystallinity.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.1
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• pp.39-42
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• 1999

Nitrogen-doped SiC(3C) (N-SiC(3C)) epliayers were grown on Si(111) substrate at $1250^{\circ}C$ using chemical vapor deposition (CVD) technique by pyrolyzing tetramethylsilane(TMS) in $H_{2}$ carrier gas. SiC(3C) layer was doped using $NH_{3}$ during the CVD growth to be n-type conduction. Physical properties of N-SiC(3C) were investigated by Fourier transform infrared (FTIR) spectroscopy, X-ray diffraction (XRD) patterns, Raman spectroscopy, cross-sectional transmission electron microscopy (XTEM), Hall measurement, and current-voltage(I-V) characteristcs of the N-SiC(3C)/Si(p) diode. N-SiC(3C) layers exhibited n-type conductivity. The n-type doping of SiC(3C) could be controlled by nitrogen dopant using $NH_{3}$ at low temperature.

• Journal of the Korean Vacuum Society
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• v.6 no.S1
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• pp.47-52
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• 1997

Metastable pseudomorphic GeSi layers grown by vapor phase epitaxy on Si(100) substrates were implanted at room temperature. The implantations were performed with 90 KeV As ions to a dose of $1\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.08}Si_{0.92}$ layers and 709 keV $BF_2^+$ ions to a dose of $3\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.06}Si_{0.94}$layers. The samples were subsequently annealed for short 10-40 s durations in a lamp furnace with a nitrogen ambient or for a long 30 min period in a vacuum tube furnace. For $Ge_{0.08}Si_{0.92}$samples annealed for a 30 min-longt duration at $700^{\circ}C$ the dopant activation can only reach 50% without introducing significant strain relaxaion whereas samples annealed for short 40s periods (at $850^{\circ}C$) can achieve more than 90% activation without a loss of strain, For $Ge_{0.06}Si_{0.94}$samples annealed for either 40s or 30min at $800^{\circ}C$ full electrical activation of the boron is exhibited in the GeSi epilayer without losing their strain. However when annealed at $900^{\circ}C$ the strain in both implanted and unimplanted layers is partly relaxed after 30min whereas it is not visibly relaxed after 40s.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.737-740
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.

• Journal of the Korean institute of surface engineering
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• v.43 no.4
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• pp.170-175
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• 2010

The GaAs epitaxial layers were grown on Si(100) substrates by molecular beam epitaxy(MBE) using the two-step method. The Si(100) substrates were cleaned with different surface cleaning method of vacuum heating, As-beam, and Ga-beam at the substrate temperature of $800^{\circ}C$. Growth temperature and thickness of the GaAs epitaxial layer were $800^{\circ}C$ and 1 ${\mu}m$, respectively. The surface structure and epitaxial growth were observed by reflection high-energy electron diffraction(RHEED) and scanning electron microscope(SEM). Just surface structure of the Si(100) substrate cleaned by Ga-beam at $800^{\circ}C$ shows double domain ($2{\times}1$). RHEED patterns of the GaAs epitaxial layers grown on Si(100) substrates with cleaning method of vacuum heating, As-beam, and Ga-beam show spot-like, ($2{\times}4$) with spot, and clear ($2{\times}4$). From SEM, it is found that the GaAs epitaxial layers grown on Si(100) substrates with Ga-beam cleaning has a high quality.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.67-68
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• 2008

In this study we have developed a packaged silicon carbide power diode with blocking voltage of 2kV. PiN diodes with 7 field limiting rings (FLRs) as an edge termination were fabricated on a 4H-SiC wafer with $30{\mu}m$-thick n-epilayer with donor concentration of $1.6\times10^{15}cm^{-3}$. From packaged PiN diode testing, we obtained reverse blocking voltage of 2kV, forward voltage drop of 4.35V at 100A/$cm^2$, on-resistance of $6.6m{\Omega}cm^2$, and about 8 nanosec reverse recovery time. These properties give a potential for the power system application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.22-27
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• 2008

Analytical models for breakdown voltage and specific on-resistance of 4H-silicon carbide Schottky diodes have been derived successfully by extracting an effective ionization coefficient $\gamma$ from ionization coefficients $\alpha$ and $\beta$ for electron and hole in 4H-SiC. The breakdown voltages extracted from our analytical model are compared with experimental results. The specific on-resistance as a function of doping concentration is also compared with the ones reported previously. Good fits with the experimental results are found for the breakdown voltage within 10% in error for the doping concentration in the range of about $10^{15}{\sim}10^{18}\;cm^{-3}$. The analytical results show good agreement with the experimental data for the specific on-resistance in the range of $3{\times}10^{15}{\sim}2{\times}10^{16}\;cm^{-3}$.

• Korean Journal of Materials Research
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• v.4 no.1
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• pp.81-89
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• 1994

Ti film of lOnm thickness and Co film of 18nm thickness were sequentially e-heam evaporated onto Si (100) substrates. Metal deposited samples were rapidly thermal-annt.aled(KTA) in thr N1 en vironment a t $900^{\circ}C$ for 20 sec. to induce the reversal of metal bilayer, so that $CoSi_{2}$ thin films could be formed. The sheet resistance measured by the 4-point probe was 3.9 $\Omega /\square$This valur was maintained with increase in annealing time upto 150 seconds, showing high thermal stab~lity. Thc XRII spectra idrn tified the silicide film formed on the Si substrate as a $CoSi_{2}$ epitaxial layer. The SKM microgr;iphs showed smooth surface, and the cross-sectional TKM pictures revealed that the layer formed on the Si substrate were composed of two Co-Ti-Si alloy layers and 70nm thick $CoSi_{2}$ epl-layer. The AES analysis indicated that the native oxide on Si subs~rate was removed by TI ar the beginning of the RTA, and Ihcn that Co diffused to clean surface of Si substrate so that epitaxial $CoSi_{2}$ film could bt, formed. In thc rasp of KTA at $700^{\circ}C$. 20sec. followed by $900^{\circ}C$, 20sec., the thin film showed lower sheet resistance, but rough surface and interface owing to $CoSi_{2}$ crystal growth. The application scheme of this $CoSi_{2}$ epilayer to VLSI devices and the thermodynarnic/kinetic mechan~sms of the $CoSi_{2}$ epi-layer formation through the reversal of Co/Ti bdayer were discussed.