• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.218-221
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• 2008

Bottom-gate microcrystalline silicon thin film transistors (${\mu}c$-Si:H TFTs) were fabricated on glass and transparent polyimide substrates by conventional 13.56 MHz RF plasma enhanced chemical vapor deposition at $200^{\circ}C$. The deposition rate of the ${\mu}c$-Si:H film is 24 nm/min and the amorphous incubation layer near the ${\mu}c$-Si:H/silicon nitride interface is unobvious. The threshold voltage of ${\mu}c$-Si:H TFTs can be improved by $H_2$ or $NH_3$ plasma pretreatment silicon nitride film.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.2
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• pp.43-51
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• 2023

In this paper, we introduce the development trends of power devices which is the key component for power conversion system in electric vehicles, and discuss the characteristics of the next-generation wide-bandgap (WBG) power devices. We provide an overview of the characteristics of the present mainstream Si insulated gate bipolar transistor (IGBT) devices and technology roadmap of Si IGBT by different manufacturers. Next, recent progress and advantages of SiC metal-oxide-semiconductor field-effect transistor (MOSFET) which are the most important unipolar devices, is described compared with conventional Si IGBT. Furthermore, due to the limitations of the current GaN power device technology, the issues encountered in applying the power conversion module for electric vehicles were described.

• KIEE International Transactions on Electrophysics and Applications
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• v.11C no.4
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• pp.99-106
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• 2001

An overview of Silicon Carbide (SiC) Static Induction Transistor (SIT) development is presented. Basic conduction mechanisms are introduced and discussed, including ohmic, exponential, and space charge limited conduction (SCLC) mechanisms. Additionally, the impact of velocity saturation and temperature effects on SCLC are reviewed. The small-signal model, breakdown voltage, power density, and different gate structures are also discussed, before a final review of published SiC SIT results. Published S-band (3-4 GHz) results include 9.5 dB of gain and output power of 120 W, and L-band (1.3 GHz) results include 400 W output power, 7.7 dB of gain, and power density of 16.7 W/cm.

• Proceedings of the KIPE Conference
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• 2019.11a
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• pp.82-84
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• 2019

본 논문에서는 Induction Heating(IH) 시스템에서 WBG 소자인 SiC MOSFET과 GaN Transistor의 Performance 비교를 통해서 소자의 적합성을 분석한다. SiC 및 GaN 소자를 직렬 공진형 컨버터로 구성된 IH 시스템에 적용하여 온도, 전압, 전류, Gate 저항 등을 고려한 도통 손실, 스위칭 손실, 역방향 도통 손실과 열 해석 프로그램을 통한 열 성능 등의 비교가 수행되며, 이를 통해 소자 적합성이 분석된다. 각 소자에 따른 IH 시스템에 대한 시뮬레이션을 수행하여, 이론적 손실 비교를 통한 소자 적합성 분석에 대한 타당성을 검증한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.204-212
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• 2020

In this study, device suitability analysis is performed by comparing the performance of SiC MOSFET and GaN Transistor, which are WBG power semiconductor devices in the induction heating (IH) system. WBG devices have the advantages of low conduction resistance, switching losses, and fast switching due to their excellent physical properties, which can achieve high output power and efficiency in IH systems. In this study, SiC and GaN are applied to a general half-bridge series resonant converter topology to compare the conduction loss, switching loss, reverse conduction loss, and thermal performance of the device in consideration of device characteristics and circuit conditions. On this basis, device suitability in the IH system is analyzed. A half-bridge series resonant converter prototype using the SiC and GaN of a 650-V rating is constructed to verify device suitability through performance comparison and verified through an experimental comparison of power loss and thermal performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.36-39
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• 2002

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays (AMLCD), allowing the integration of both active matrix and driving circuit on the same substrate (normally glass). As high temperature process is not used for glass substrate because of the low softening points below 450$^{\circ}C$. However, high temperature process is required for getting high crystallization volume fraction (i.e. crystallinity). A poly-Si thin film transistor has been fabricated to investigate the effect of high temperature process on the molybdenum (Mo) substrate. Improve of the crystallinity over 75% has been noticed. The properties of structural and electrical at high temperature poly-Si thin film transistor on Mo substrate have been also analyzed using a sputtering method

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.589-592
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• 1999

This paper describes direct $\mu$C-Si/CaF$_2$/glass thin film growth by RPCVD system in a low temperature for thin film transistor (TFT), photovoltaic devices. and sensor applications. Experimental factors in a low temperature direct $\mu$ c-Si film growth are presented in terms of deposition parameters: SiH$_4$/H$_2$ ratio, chamber total pressure, substrate temperature, rf power, and CaF$_2$ buffer layer. The structural and electrical properties of the deposited films were studied by means of Raman spectroscopy, I-V, L-I-V, X-ray diffraction analysis and SEM. we obtain a crystalline volume fraction of 61%, preferential growth of (111) and (220) direction, and photosensitivity of 124. We achieved the improvement of crystallinity and electrical property by using the buffer layers of CaF$_2$ film.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.13-17
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• 2006

Pentacene channel for organic thin film transistor was deposited on the SiOC film by thermal evaporation. The growth of pentacene is related with the Diels-Alder reaction and the nucleophilic reaction by the thermal induction. The surface is an important factor to control the recursive Diels-Alder reaction for growing of pentacene on SiOC far The terminal C=C double bond of pentacene molecule was broken easily as a result of attack of the nucleophilic reagents on the surface of SiOC film. The nucleophilic reaction can be accelerated by increasing temperature on surface, and it maks pentacene to grow hardly on the SiOC film with a flow rate ratio of $O_2/(BTMSM+O_2)=0.5$ due to its inorganic property. The nucleophlic reaction mechanism is $SN_2(bimolecular nucleophilic substitution)$ type.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• Transactions on Electrical and Electronic Materials
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• v.1 no.2
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• pp.7-11
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• 2000

a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.