• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2019년도 추계학술대회
• /
• pp.87-89
• /
• 2019

본 논문에서는 직렬 연결된 스위칭 소자에서 발생할 수 있는 전압 불평형의 원인을 분석하고 이를 제거할 수 있는 능동 게이트 구동 기법을 제안한다. 제안하는 방법은 스위치의 턴오프 경로에 트랜지스터를 추가하여 전압 불평형 정도에 따라 각 소자의 스위칭 속도를 조절함으로써 전압 불평형을 제거한다. 제안하는 방법의 확인을 위하여 SiC MOSFET을 이용한 전력변환회로를 대상으로 모의실험을 실시하였고, 제안하는 방법이 전압 불평형의 제거에 효과적임을 검증하였다.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2020년도 전력전자학술대회
• /
• pp.22-24
• /
• 2020

본 논문은 11kW급 양방향 탑재형 충전기를 위한 CLLLC 공진 컨버터 설계에 대하여 발표한다. CLLLC 공진 컨버터의 공진 탱크 설계하였으며, 고효율화를 위하여 SiC-MOSFET을 사용하고, 배터리 전압에 따라 링크전압 가변 알고리즘과 동기정류기를 적용하였다. 그 결과를 바탕으로 프로토타입을 제작하여 실험한 결과를 발표한다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 추계학술대회 논문집
• /
• pp.55-55
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권2호
• /
• pp.95-102
• /
• 2001

Hafnium oxide thin films for gate dielectric were deposited at $300^{\circ}C$ on p-type Si (100) substrates by plasma enhanced chemical vapor deposition (PECVD) and annealed in $O_2$ and $N_2$ ambient at various temperatures. The effect of hydrogen treatment in 4% $H_2$ at $350^{\circ}C$ for 30 min on the electrical properties of $HfO_2$for gate dielectric was investigated. The flat-band voltage shifts of $HfO_2$capacitors annealed in $O_2$ambient are larger than those in $N_2$ambient because samples annealed in high oxygen partial pressure produces the effective negative charges in films. The oxygen loss in $HfO_2$films was expected in forming gas annealed samples and decreased the excessive oxygen contents in films as-deposited and annealed in $O_2$ or $N_2$ambient. The CET of films after hydrogen forming gas anneal almost did not vary compared with that before hydrogen gas anneal. Hysteresis of $HfO_2$films abruptly decreased by hydrogen forming gas anneal because hysteresis in C-V characteristics depends on the bulk effect rather than $HfO_2$/Si interface. The lower trap densities of films annealed in $O_2$ambient than those in $N_2$were due to the composition of interfacial layer becoming closer to $SiO_2$with increasing oxygen partial pressure. Hydrogen forming gas anneal at $350^{\circ}C$ for samples annealed at various temperatures in $O_2$and $N_2$ambient plays critical role in decreasing interface trap densities at the Si/$SiO_2$ interface. However, effect of forming gas anneal was almost disappeared for samples annealed at high temperature (about $800^{\circ}C$) in $O_2$ or $N_2$ambient.

• 한국전기전자재료학회논문지
• /
• 제23권7호
• /
• pp.513-516
• /
• 2010

In this work, a study is presented of the static characteristics of 4H-SiC DMOSFETs obtained by adjustment of the p-base region. The structure of this MOSFET was designed by the use of a device simulator (ATLAS, Silvaco.). The static characteristics of SiC DMOSFETs such as the blocking voltages, threshold voltages, on-resistances, and figures of merit were obtained as a function of variations in p-base doping concentration from $1\;{\times}\;10^{17}\;cm^{-3}$ to $5\;{\times}\;10^{17}\;cm^{-3}$ and doping depth from $0.5\;{\mu}m$ to $1.0\;{\mu}m$. It was found that the doping concentration and the depth of P-base region have a close relation with the blocking and threshold voltages. For that reason, silicon carbide DMOSFET structures with highly intensified blocking voltages with good figures of merit can be achieved by adjustment of the p-base depth and doping concentration.

• 전기전자학회논문지
• /
• 제24권1호
• /
• pp.170-177
• /
• 2020

본 논문은 HF/LF 변조 방법을 적용한 ANPC (active neutral point clamped) 인버터의 스위치 개방 고장에 대응하기 위한 허용 제어 방법을 제안한다. 기존 Si 기반 인버터에 비해 SiC MOSFET과 Si IGBT로 구성된 ANPC 인버터는 시스템의 효율이 높고 출력 품질이 우수하다. HF/LF 변조는 커뮤테이션 루프를 줄일 수 있어 MW 급 대용량 인버터를 위해 사용되는 변조 기법이다. MW 급 인버터의 스위치 개방 고장은 부하에 심각한 손상을 입히며, 인버터가 동작을 멈출 경우 막대한 경제적 손실을 야기한다. 제안하는 스위치 개방 고장의 허용 제어 기술은 ANPC 인버터의 지속적인 운전을 가능하게 하며 신뢰성을 향상 시킨다. 제안하는 기법의 성능은 시뮬레이션 결과를 통해 검증한다.

• KIEE International Transactions on Electrophysics and Applications
• /
• 제2C권5호
• /
• pp.258-261
• /
• 2002

Electrical forming dependent current-voltage (I-V) and numerically derived differential conductance(dI／dV) characteristics have been presented in the multi-layer nano-crystalline silicon／oxygen (no-Si／O) superlattice. Distinct staircase-like features, indicating the presence of resonant tunnel barriers, are clearly observed in the dc I-V characteristics. Also, all samples showed a continuous change in current and zero conductivity around OV corresponding to the Coulomb blockade in the calculated dI／dV-V curve. Also, Ra-man scattering measurement showed the presence of a nano-crystalline Si structure. This result becomes a step in the right direction for the fabrication of silicon-based optoelectronic and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in high speed and low power silicon MOSFET devices of the future.

• 한국진공학회지
• /
• 제22권5호
• /
• pp.245-249
• /
• 2013

MOSFET 구조의 차세대 Oxide 박막으로 주목받고 있는 $HfO_X$박막을 rf magnetron sputter를 이용하여 Si(100) 기판 위에 증착하였다. 증착시 산소의 유량을 5, 10, 15 sccm으로 변화를 주며 증착하였고 이후 furnace에서 400부터 $800^{\circ}C$까지 질소분위기로 열처리 하였다. 실험결과 $HfO_X$ 박막의 전기적 특성은 산소유량 증가에 따라 누설전류 특성이 향상되었으나, 열처리 온도가 증가함에 따라서는 감소하였다. 특히, 이 논문에서는 Nano-indenter와 AFM으로 $HfO_X$ 박막의 nanomechanics 특성을 측정하였다. 측정 결과에 의하면 열처리 온도가 증가함에 따라 최대 압입력을 기준으로 최대 압입 깊이가 24.9 nm에서 38.8 nm로 증가하였으며 특히 $800^{\circ}C$ 열처리된 박막에서 압입 깊이가 급격하게 증가하였다. 이러한 압입 깊이의 급격한 증가는 박막내 응력 완화에 의한 스트레스 변화로 예상되며, 그 원인으로 증착시 박막내 포함된 산소가 열처리 조건에 의해 빠져나감에 의한 것으로 판단된다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.143.1-143.1
• /
• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
• /
• pp.122-126
• /
• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.