• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2014년도 추계학술대회 논문집
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• pp.104-105
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• 2014

마이크로 패턴된 Au 전극사이에 얼라인된 Tellurium (Te) 나노리본들이 의도한 모양과 배열방식을 가지고 리쏘그래피 패턴 전해증착 (Lithographically patterned nanowier electrodepositon, LPNE) 방법에 의해 4인치 Si wafer 배치로 합성되었다. 합성된 Te 나노리본은 수 센티미터의 길이를 가지고, 그 두께와 폭 역시 작업 전극으로 사용되는 Si wafer위에 증착된 Ni의 두께와 전해증착 시간에 의해 쉽게 제어될 수 있다. $3{\mu}m$의 간격을 갖는 Au 전극 사이에 얼라인된 두께 ~100nm의 Te 나노리본들은 전해증착에 의해 그 폭이 제어되었고, 각각의 다른 폭을 갖는 증착된 하나의 Te 나노리본들의 IV 및 FET 측정을 통하여 나노리본 폭의 변화에 따른 전기적 특성 (비저항, FET 이동도 및 FET 캐리어 농도)이 평가되었다.

• 신재생에너지
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• 제2권2호
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• pp.4-8
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient Reff lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2006년도 춘계학술대회
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• pp.183-186
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient $R_{eff}$ lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 한국전기전자재료학회논문지
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• 제14권3호
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• pp.223-227
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• 2001

In this paper, the authors present the fabrication of high-yield Si thin-membranes by electrochemical etch-stop in tetramethyl ammonium hydroxide (TMAH): isopropyl alcohol (IPA):pyrazine solutions. The current-voltage (I-V) characteristics of n- and p-type Si in TMAH:IPA;pyrazine solutions were analysed, repsectively. Open circuit potential (OCP)and passivation potential (PP) of n- and p-type Si, respectively, were obtained and applied potential was selected between n- and p-type Si PPs. The electrochemical etch-stop method was applied to the fabrication of 801 micro-membranes with 20.0 $\mu\textrm{m}$ thickness on a 5" Si wafer. The average thickness of fabricated 801 micro-membranes on one wafer 20.03$\mu\textrm{m}$ and the standard deviation was ${\pm}$0.26$\mu\textrm{m}$. The Si surface of the etch-stopped micro-membranes was extremely flat with no noticeable taper or nonuniformity. The results indicate that use of the electrochemical etch-stop method for the etching of Si in TMAH:IPA;pyrazine solutions provides a powerful and versatile alternative process for fabricating high-yield Si micro-membranes.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.226-226
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• 2013

Si is a dominant solar material, which is the second most abundant element in the earth giving a benefit in the aspect in cost with low toxicity. However, the inherent limit of Si has an indirect band gap of 1.1 eV resulting in the limited optical absorption. Therefore, a critical issue has been raised to increase the utilization of the incident light into the Si absorber. The enhancement of light absorption is a crucial to improve the performances and thus relieves the cost burden of Si photovoltaics. For the optical aspect, an efficient design of a front surface, where the incident light comes in, has been intensively investigated to improve the performance of photon absorption. Lambertian light trapping can be attained when the light active surface is ideally rough to increase the optical length by about 50 compared to a planar substrate. This suggests that an efficient design may reduce thickness of the Si absorber from the conventional 100~300 ${\mu}m$ to less than 3 ${\mu}m$. Theoretically, a hole-array structure satisfies an equivalent efficiency of c-Si with only one-twelfth mass and one-sixth thickness. Various approaches have been applied to improve the incident light utilization in a Si absorber using textured structures, periodic gratings, photonic crystals, and nanorod arrays. We have designed hole and pillar structured Si absorbers. Four-different Si absorbers have been simultaneously fabricated on an identical Si wafer with hole arrays or pillar arrays at a fixed depth of 2 ${\mu}m$. We have found that the significant enhanced solar cell performances both for the hole arrayed and pillar arrayed Si absorbers compared to that of a planar Si wafer resulting from the effective improvement in the quantum efficiencies.

• 한국재료학회지
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• 제11권7호
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• pp.556-561
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• 2001

실리사이드반웅을 이용하여 니켈모노실리사이드의 양측계면에 단결정실리콘을 적층시켜 전도성이 우수하며 식각특성이 달라 MEMS용 기판으로 채용이 가능한 SOS (Silicon-on-Silicide) 기판을 제작하였다. 실리콘 기판 전면에 Ni를 열증착법으로$ 1000\AA$두께로 성막하고, 실리콘 기판 경면과 맞블여 후 $300~900^{\circ}C$온도범위에서 15시간동안 실리사이드 처리하여 니켈모노실리사이드가 접합매체로 되는 기판쌍들을 완성하였다. 완성된 기판쌍들은 IR (infrared) 카메라를 이용하여 비파괴적으로 접합상태를 확인하고. 주사전자현미경 (scaning electron microscope)과 투과전자현미경 (tranmission electron microscope)을 이용하여 수직단면 미세구조를 확인하였다. Ni 실리사이드의 상변화가 일어나는 온도를 제외하고는 Si NiSi ∥Si 기판쌍은 기판전면에 52%이상 완전접합이 진행되었음을 확인하였고 생성 실리사이드의 두께에 따라 나타나는 명암부에 비추어 기판쌍 중앙부에 두꺼운 니켈노실리아드가 형성되었다고 판단되었다. 완성된 Si NiSi ∥ Si 기판쌍을 SBM 수직단면에 의괘 확인한 결과 접합이 완성된 기판중심부의 접합계면은 $1000\AA$ 두께의 NiSi가 균일하게 형성되었으며 배율 30,000배의 해상도에서 계면간 분리부분없이 완전한 접합이 진행되었음을 확인하였다. 반면 기판쌍 에지 (edge)부분에는 실리사이드가 헝성되지 않은 비접합상태가 발견되었다. 수직단면루과전자현미경 결과물에 근거하여 접합된 중심부에서는 피접합되는 실리콘의 경면과 니켈이 성막된 실리콘 경면 상부계면에 10-20$\AA$의 비정질막이 발견되었으며, 산화막으로 추정되는 이 막이 접합률을 현저히 저하시키는 것을 확인하였다. 접합이 진행되지 않은 에지부는 이러한 산화막이 열처리 진행중 급격히 성장하여 피접합 실리콘층의 분리가 발생하였다. 따라서 Si NiSi ∥Si 기판쌍의 접합률을 향상시키기 위해서는 피접합 실리콘 계면과 Ni 상부층간의 비정질부를 적극적으로 제거하여야 함을 알 수 있었다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.128.1-128.1
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• 2011

In amorphous silicon and crystalline silicon(a-Si:H/c-Si) heterojuction solar cells, intrinsic hydrogenated amorphous silicon(a-Si:H) films play an important role to passivate the crystalline silicon wafer surfaces. We have studied the correlation between the surface passivation quality and nature of the Si-H bonding at the a-Si:H/c-Si interface. The samples were obtained by VHF-CVD under different deposition conditions. The passivation quality and analysis of all structures studied was performed by means of quasi steady state photoconductance(QSSPC) methods and fourier transform infrared spectrometer(FTIR) measurements respectively.

• 한국재료학회지
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• 제23권6호
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• pp.322-328
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• 2013

The relationship the between electrical properties and surface roughness (Ra) of a wet-etched silicon wafer were studied. Ra was measured by an alpha-step process and atomic force microscopy (AFM) while varying the measuring range $10{\times}10$, $40{\times}40$, and $1000{\times}1000{\mu}m$. The resistivity was measured by assessing the surface resistance using a four-point probe method. The relationship between the resistivity and Ra was explained in terms of the surface roughness. The minimum error value between the experimental and theoretical resistivities was 4.23% when the Ra was in a range of $10{\times}10{\mu}m$ according to AFM measurement. The maximum error value was 14.09% when the Ra was in a range of $40{\times}40{\mu}m$ according to AFM measurement. Thus, the resistivity could be estimated when the Ra was in a narrow range.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.57-57
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• 2003

• ETRI Journal
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• 제43권5호
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• pp.909-915
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• 2021

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer-scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3-㎛ bowing was observed using the 725-㎛-thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4×10⁷ cm^-2. For lattice-matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725-㎛-thick Si substrate can be used for the large-scale integration of GaAs on Si with less bowing and low TDD.