• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.539-542
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• 2001

In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO$_2$layer on the suppression of macrostep formation during high temperature anneal. The cap oxide layer was found to be efficient for suppression of macrostep formation even though the annealing temperature is as high as the melting point of SiO$_2$. The thin cap oxide layer (10nm) was evaporated during anneal then the macrosteps were formed on SiC substrate. On the other hand the thicker cap oxide layer (50nm) remains until the anneal process ends. In that case, the surface was smoother and the macrosteps were rarely formed. The thermally-grown oxide layer is found to be a good material for the suppression of macrostep formation because of its feasibility of growing and processing. Moreover, we can choose a proper oxide thickness considering the evaporate rate of SiO$_2$at the given temperature.

• Journal of the Korean Vacuum Society
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• v.5 no.2
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• pp.113-118
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• 1996

Aligning a cathode tip at the center of a gate hole is important in gated filed emission devices. We have fabricated a silicon field emitter using a following process so that a cathode and a gate hole are automatically aligned . After forming silicon tips on a silicon wafer, the wafer was covered with the $SiO_2$, gate metal, and photoresistive(PR) films. Because of the viscosity of the PR films, a spot where cathode tips were located protruded above the surface. By ashing the surface of the PR film, the gate metal above the tip apex was exposed when other area was still covered with the PR film. The exposed gate metal and subsequenlty the $SiO_2$ layer were selectively etched. The result produced a field emitter in which the gate film was in volcano shape and the cathode tip was located at the center of the gate hole. Computer simulation showed that the volcano shape and the cathode tip was located at the center of the gat hole. Computer simulation showed that the volcano shape emitter higher current and the electron beam which was focused better than the emitter for which the gate film was flat.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• Journal of the Korean Vacuum Society
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• v.10 no.2
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• pp.267-274
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• 2001

Removal of Cr, Ni and Cu impurities on Si surfaces using remote plasma-excited hydrogen was investigated. Si surfaces were contaminated intentionally by acetone with low purity. To determine the optimum process condition, remote plasma-excited hydrogen cleaning was conducted for various rf-powers and plasma exposure times. After remote plasma-excited hydrogen cleaning, Si surfaces were analyzed by Total X-ray Reflection Fluorescence(TXRF), Surface Photovoltage(SPV) and Atomic Forece Microscope(AFM). The concentrations of Cr, Ni and Cu impurities were reduced and the minority carrier lifetime increased after remote plasma-excited hydrogen. Also RMS roughness decreased by more than 30% after remote plasma-excited hydrogen cleaning. AFM analysis results also show that remote plasma-excited hydrogen cleaning causes no damage to the Si surface. TXRF analysis results show that remote plasma-excited hydrogen cleaning is effective in eliminating metallic impurities from Si surface only if it is performed under an optimum process conditions. The removal mechanism of the Cr, Ni and Cu impurities using remote plasma-excited hydrogen treatments is proposed to be the lift-off during removal of underlying chemical oxides.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2001.11a
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• pp.68-68
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• 2001

Thin films of polycrystalline silicon (poly-Si) is a promising material for use in large-area electronic devices. Especially, the poly-Si can be used in high resolution and integrated active-matrix liquid-crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs) because of its high mobility compared to hydrogenated _amorphous silicon (a-Si:H). A number of techniques have been proposed during the past several years to achieve poly-Si on large-area glass substrate. However, the conventional method for fabrication of poly-Si could not apply for glass instead of wafer or quartz substrate. Because the conventional method, low pressure chemical vapor deposition (LPCVD) has a high deposition temperature ($600^{\circ}C-1000^{\circ}C$) and solid phase crystallization (SPC) has a high annealing temperature ($600^{\circ}C-700^{\circ}C$). And also these are required time-consuming processes, which are too long to prevent the thermal damage of corning glass such as bending and fracture. The deposition of silicon thin films on low-cost foreign substrates has recently become a major objective in the search for processes having energy consumption and reaching a better cost evaluation. Hence, combining inexpensive deposition techniques with the growth of crystalline silicon seems to be a straightforward way of ensuring reduced production costs of large-area electronic devices. We have deposited crystalline poly-Si thin films on soda -lime glass and SiOz glass substrate as deposited by PVD at low substrate temperature using high power, magnetron sputtering method. The epitaxial orientation, microstructual characteristics and surface properties of the films were analyzed by TEM, XRD, and AFM. For the electrical characterization of these films, its properties were obtained from the Hall effect measurement by the Van der Pauw measurement.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.2023-2025
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• 2002

We have fabricated a novel vertical trench-Hall device sensitive to the magnetic field parallel to the sensor chip surface. The vertical trench-Hall device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 350 V/AT is measured.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.411-414
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• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PT layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PT layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PT layer of c-axial orientation rained thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PT layer were measured, too.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.815-819
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• 1998

The silicon-nirtide membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PRO($PbTiO_3$ ) layer for a IR detection was coated on the membrane and its characteristics were measured. The a attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer were eliminated through the method of bonding/etching of silicon wafer. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by the PTO layer were measured, too.

• Journal of the Korean Applied Science and Technology
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• v.32 no.2
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• pp.232-239
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• 2015

In this paper, we study the dry transfer technology utilizing PDMS (Polydimethylsiloxane) stamp of a large single-layer graphene grown on Cu-foil as catalytic metal by using Chemical Vapor Deposition (CVD). By changing the surface property of the target substrate through $UV/O_3$ treatment, we can transfer the graphene on the target substrate while minimizing mechanical damages of graphene layer. Multi-layer (1~4 layers) graphene was stacked on $SiO_2/Si$ wafer successfully by repeating thetransfer method/process and then optical transmittance and sheet resistance of graphene layers have been measured as a quality assessment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.553-556
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• 1999

This paper presents a proper condition to achieve above 19 % conversion efficiency using PC1D simulator. Cast poly-Si wafers with resistivity of 1 $\Omega$-cm and thickness of 250 ${\mu}{\textrm}{m}$ were used as a starting material. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 ${\mu}{\textrm}{m}$, front surface recombination velocity 100 cnt/s, sheet resistivity of emitter layer 100 $\Omega$/$\square$, BSF thickness 5 ${\mu}{\textrm}{m}$, doping concentration 5$\times$10$^{19}$ cm$^3$ . Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %. Further details of simulation parameters and their effects to cell characteristics are discussed in this paper.