• ETRI Journal
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• v.43 no.5
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• pp.909-915
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• 2021

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer-scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3-㎛ bowing was observed using the 725-㎛-thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4×10⁷ cm^-2. For lattice-matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725-㎛-thick Si substrate can be used for the large-scale integration of GaAs on Si with less bowing and low TDD.

• Korean Journal of Materials Research
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• v.8 no.9
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• pp.837-842
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• 1998

As the size of the integrated circuit is scaled down the importance of Si cleaning has been emphasized. One of the major concerns is abut the removal of metallic impurities such as Cu and Fe on Si surface. In this study, we intentionally contaminated Cu and Fe on the Si wafers and cleaned the wafer by cleaning splits of the chemical mixture of $\textrm{H}_2\textrm{O}_2$ and HF and the combination of HF treatment with UV/$\textrm{O}_3$ treatment. The contamination level was monitored by TXRF. Surface microroughness of the Si wafers was measured by AFM. The Si wafer surface was examined by SEM. AES analysis was carried out to analyze the chemical composition of Cu impurities. The amount of Cu impurities after intentional contamination was abut the level of $\textrm{10}^{14}$ atoms/$\textrm{cm}^2$. The amount of Cu was decreased down to the level of $\textrm{10}^{10}$ atoms/$\textrm{cm}^2$ by cleaning splits. The repeated treatment exhibited better Cu removal efficiency. The surface roughness caused by contamination and removal of Cu was improved by repeated treatment of the cleaning splits. Cu were adsorbed on Si surface not in a thin film type but in a particle type and its diameter was abut 100-400${\AA}$ and its height was 30-100${\AA}$. Cu was contaminated on Si surface by chemical adsorption. In the case of Fe the contamination level was $\textrm{10}^{13}$ atoms/$\textrm{cm}^2$ and showed similar results of above Cu cleaning. Fe was contaminated on Si surface by physical adsorption and as a particle type.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.616-621
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• 2009

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.

• Transactions on Electrical and Electronic Materials
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• v.2 no.2
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• pp.26-31
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• 2001

This paper presents the electrochemical etch-stop characteristics of single-crystal Si(001) wafers in tetramethyl ammonium hydroxide(TMAH):isopropyl alcohol(IPA):pyrazine solutions. The addition of pyrazine to TMAH:IPA solutions increased the etch rate of (100) Si, thus the etching time required by the etch-stop process shortened. The current-voltage(I-V) characteristics of n- and p-type Si in TMAH:IPA:pyrazine solutions were obtained, respectively. Open circuit potential(OCP) and passivation potential(PP) of n- and p-type Si, respectively, were obtained and applied potential was selected between n- and p-type Si PPs. The electrochemical etch-stop method was used to fabricate 801 microdiaphragms of 20 ${\mu}{\textrm}{m}$ thickness on a 5-inch Si wafer. The average thickness of fabricated 801 microdiaphragms on one Si wafer was 20.03 ${\mu}{\textrm}{m}$ and the standard deviation was $\pm$0.26 ${\mu}{\textrm}{m}$. The Si surface of the etch-stopped microdiaphragm was extremely flat with no noticeable taper or nonuniformity.

• Journal of the Korean Society for Heat Treatment
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• v.26 no.4
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• pp.178-184
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• 2013

The effects of thickness and surface grinding condition on the fracture strength of Si wafer with a thickness under $100{\mu}m$ were investigated. Fracture strength was measured by ball breaker test for about 330 dies (size: $4mm{\times}4mm$) per each wafer. For statistical analysis of the fracture strength, scale factor was determined from Weibull plot. Ball breaker fracture strength was observed to increase with decreasing thickness of silicon die. For the silicon dies of different surface conditions, ball breaker fracture strength was high in the order of polished, ground (#4800), and ground (#320 grit) specimen. Probabilistic fracture strength (i.e., scale factor) increased with decreasing surface roughness of silicon die.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.225-232
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• 2011

Reactive ion etching (RIE) technique for maskless surface texturing of mc-silicon solar wafers has been applied and succeed in fabricating a grass-like black-silicon with an average reflectance of $4{\pm}1%$ in a wavelength range of 300~1,200 nm. In order to investigate the optimized texturing conditions for mass production of high quantum efficiency solar cell Surface characteristics such as the spatial distribution of average reflectance, micrscopic surface morphology and minority carrier lifetime were monitored for samples from saw-damaged $15.6{\times}15.6\;cm^2$ bare wafer to key-processed wafers as well as the mc-Si solar cells. We observed that RIE textured wafers reveal lower average reflectance along from center to edges by 1% and referred the origin to the non-uniform surface structures with a depth of 2 times deeper and half-maximum width of 3 times. Samples with anti-reflection coating after forming emitter layer also revealed longer minority carrier lifetime by 40% for the edge compared to wafer center due to size effects. As results, mc-Si solar cells with RIE-textured surface also revealed higher efficiency by 2% and better external quantum efficiency by 15% for edge positions with higher height.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.389-392
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• 1999

We employed cobalt-disilicide for high-speed logic devices. We prepared stable and low resistant $CoSi_2$ through typical fabrication process including wet cleaning and rapid thermal process (RTP). We sputtered 15nm thick cobalt on the wafer and performed RTP annealing 2 times to obtain 60nm thick $CoSi_2$. We observed spherical shape voids with diameter of 40nm in the surface and inside $CoSi_2$ layers. The voids resulted in taking over abnormal junction leakage current and contact resistance values. We report that the voids in $CoSi_2$ layers are resulted from surface pits during the ion implantation previous to deposit cobalt layer. Silicide reaction rate around pits was enhanced due to Gibbs-Thompson effects and the volume expansion of the silicidation of the flat active regime trapped dimples. We confirmed that keeping the buffer oxide layer during ion implantation and annealing the silicon surface after ion implantation were required to prevent void defects in CoSi$_2$ layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.346-349
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• 2002

High Power and high dose ion implantation is essentially needed to make power MOSFET devices based on SiC wafers, because the diffusivities of the impurities such as Al, N, p, B in SiC crystal are very low. In addition, it is needed high temperature annealing for electrical activation of the implanted species. Due to the very high annealing temperature, the surface morphology after electrical activation annealing becomes very rough. We have found the different surface morphologies between implanted and unimplanted region. The unimplanted region showed smoother surface morphology It implies that the damage induced by high energy ion implantation affects the roughening mechanism. Some parts of Si-C bonding are broken in the damaged layer, s\ulcorner the surface migration and sublimation become easy. Therefore the macrostep formation will be promoted. N-type 4H-SiC wafers, which were Al ion implanted at acceleration energy ranged from 30kev to 360kev, were activated at 1600$^{\circ}C$ for 30min. The pre-activation annealing for damage relaxation was performed at 1100-1500$^{\circ}C$ for 30min. The surface morphologies of pre-activation annealed and activation annealed were characterized by atomic force microscopy(AFM).

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.11
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• pp.1631-1636
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• 2010

In this study, we demonstrate a nano-scale lithograph obtained on localized (100) silicon (p-type) surface using by modified AFM (Atomic force microscope) apparatuses and by adopting controlling methods. AFM-based experimental apparatuses are connected to a customized pulse generator that supplies electricity between the conductive tip and the silicon surface, while maintaining a constant humidity throughout the lithography process. The pulse durations are controlled according to various experimental conditions. The electrochemical reaction induced by the pulses occurs in the gap between the conductive tip and silicon surface and result in the formation of nanoscale oxide particles. Oxide particles with various heights and widths can be created by AFM surface modification; the size of the oxide particle depends on the pulse durations and the applied electrical conditions under a humid environment.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.11a
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• pp.37-38
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• 2007

Si Interlayer의 두께가 DLC (Diamond-like Carbon) 박막의 조도 및 미세 조직에 미치는 영향을 AFM 및 TEM을 이용하여 조사하였다. DLC 박막은 이온빔 소스를 이용하여 벤젠가스를 플라즈마 분해하여 기판에 증착하였고 기판에는 2kV의 펄스전원을 인가하였다. 기판은 Si Wafer와 초경을 이용하였으며 초경의 경우 평균조도가 20nm이하가 되도록 연마하여 사용하였다. Si Interlayer는 스퍼터링 소스를 이용하여 제조하였고 증착 시간에 따라 두께를 달리하여 약 90nm까지 변화시켰다. Si Interlayer만 증착하였을 경우 조도에 큰 차이를 나타내었으나 Interlayer 위에 DLC가 코팅되면 조도가 감소하여 Si 두께와는 상관이 없는 것으로 나타났다. 본 연구에서는 Interlayer에 두께에 따른 조도변화와 함께 피막의 조직 및 경도 변화 등에 대해 고찰하였다.