• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.63-67
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• 2008

3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to $30{\mu}m\;or\;50{\mu}m$ thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.7 s.238
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• pp.983-989
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• 2005

The effects of mechanical parameters on the characteristics of chemical mechanical polishing(CMP) can be directly evaluated by friction force. The piezoelectric quartz sensor for friction force measurement was installed, and friction force could be detected during CMP process. Furthermore, friction energy can be calculated by multiplying relative velocity by integration of the friction force throughout the polishing time. $SiO_2$ slurry for interlayer dielectric(ILD) CMP was used in this experiment to consider the relation of frictional characteristics and polishing results. From this experiment, it is proven that the friction energy is an essential factor of removal rate. Also, the friction force is related to removal amount per unit length(dH/ds) and friction energy has corelation to the removal rate(dH/dt) and process temporature. Moreover, within wafer non-unifornity(WIWNU) is related to coefficient of friction because of the mechanical moment equilibrium. Therefore, the prediction of polishing result would be possible by measuring friction force.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Journal of the Korean Vacuum Society
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• v.9 no.2
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• pp.102-109
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• 2000

It is difficult to meet the cleanliness requirement of $10^{10}/\textrm{cm}^2$ for the giga level device fabrication with mechanical cleaning techniques like scrubbing which is widely used to remove the particles generated during Chemical Mechanical Polishing (CMP) processes. Therefore, the second cleaning process is needed to remove metallic contaminants which were not completely removed during the mechanical cleaning process. In this paper the experimental results for the removal of the metallic contaminants existing on the wafer surface using remote plasma $H_2$ cleaning and UV/$O_3$ cleaning techniques are reported. In the remote plasma $H_2$ cleaning the efficiency of contaminants removal increases with decreasing the plasma exposure time and increasing the rf-power. Also the optimum process conditions for the removal of K, Fe and Cu impurities which are easily found on the wafer surface after CMP processes are the plasma exposure time of 1min and the rf-power of 100 W. The surface roughness decreased by 30-50 % after remote plasma $H_2$ cleaning. On the other hand, the highest efficiency of K, Fe and Cu impurities removal was achieved for the UV exposure time of 30 sec. The removal mechanism of the metallic contaminants like K, Fe and Cu in the remote plasma $H_2$ and the UV/$O_3$ cleaning processes is as follows: the metal atoms are lifted off by $SiO^*$ when the $SiO^*$is evaporated after the chemical $SiO_2$ formed under the metal atoms reacts with $H^+ \; and\; e^-$ to form $SiO^*$.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.35-37
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• 2005

100, 200nm 크기의 colloidal silica 각각에 나노 ceria 입자를 수열합성법으로 코팅하였다. Colloidal silica 입자에 ceria를 코팅 시 slurry의 pH조절과 수열처리에 이용하여 silica에 ceria가 코팅됨을 TEM과 zeta-potential을 이용하여 확인하였다. 연마 슬러리의 분산 안정성과 연마효율을 높이기 위하여 슬러리의 pH 는 9로 하였으며, 이때의 zeta-potential 값은 -25 mV이었다. 1 wt%로 제조된 연마슬러리를 이용하여, 4 inch $SiO_2$, $Si_3N_4$ wafer를 압력변화에 따른 연마특성을 관찰 하였다. Ceria coated colloidal silica 100 nm, 200 nm와 commercial한 $CeO_2$입자를 연마압력 6 psi로 oxide film을 연마한 결과 연마율이 각각 2490 ${\AA}/min$, 4200 ${\AA}/min$, 4300 ${\AA}/min$으로 측정되었다. 또한 $SiO_2$, $Si_3N_4$ film의 6 psi압력에서 ceria coated colloidal silica 100 nm, 200 nm와 commercial 한 $CeO_2$입자의 선택비는 3, 3.8, 6.7 이었다. 입자크기가 클수록 연마율이 높으며, Preston equation을 따라 연마 압력과 연마율이 비례하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.86-87
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• 2007

The dispersive method of white-light interferometry is proper for in-line 3-D inspection of dielectric thin-film thickness to be used in the semiconductor and flat-panel display industry. This research is the measurement application of CMP patterned wafer. The results describe 3-D and 2-D profile of the step height during polishing time.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.47-51
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• 2013

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.11
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• pp.46-56
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• 1996

Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.