• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.221.1-221.1
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• 2015

The vapor-liquid-solid (VLS) method, where the "liquid" catalytic droplets collecting atoms from vapor precursors build the solid crystal layers via supersaturation, is a ubiquitous technique to synthesize 1-dimensional nanoscale materials. However, the lack of fundamental understanding of chemical information governing the process inhibits the rational route to the structural programming. By combining the in situ or operando IR spectroscopy with post-growth high resolution electron microscopy, we show the strong correlation between the surface chemical species concentration and nanowire structures. More specifically, the critical role of surface adsorbed hydrogen, generated from the decomposition of Si2H6 precursor on the interplay between nanowire / kinking and the defect propagation is demonstrated. Our results show that adsorbed hydrogen atoms are responsible for selecting -oriented growth and indicate that a twin boundary imparts structural coherence. The twin boundary, only continuous at / kinks, reduces the symmetry of the trijunction and limits the number of degenerate directions available to the nanowire. These findings constitute a general approach for rationally engineering kinking superstructures and also provide important insight into the role of surface chemical bonding during VLS synthesis.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1343-1348
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• 2014

The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, $I_{on}/I_{off}$ and fringing capacitance using TCAD simulations. Molybdenum based gate electrode showed significant improvement in terms of high drive current, Low DIBL and high $I_{on}/I_{off}$. The noise power sepctral density is reduced by characterizing the device at higher frequencies. Silicon Nanowire with Si3N4 spacer decreases the drain current spectral density which interms reduces the fringing fields there by decreasing the flicker noise.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.441-442
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• 2010

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.3
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• pp.185-191
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• 2017

Cadmium compounds with one dimension (1D) nanostructures have attracted attention for their excellent electrical and optical properties. In this study, vertically aligned CdTe-Si nanostructures with high density were synthesized by several simple chemical reactions. First, l D Te nanostructures were synthesized by silver assisted chemical Si wafer etching followed by a galvanic displacement reaction of the etched Si nanowires. Nanowire length was controlled from 1 to $25{\mu}m$ by adjusting etching time. The Si nanowire galvanic displacement reaction in $HTeO_2{^+}$ electrolyte created hybrid 1D Te-branched Si nanostructures. The sequential topochemical reaction resulted in $Ag_2Te-Si$ nanostructures, and the cation exchange reaction with the hybrid 1D Te-branched Si nanostructures resulted in CdTe-Si nanostructures. Wet chemical processes including metal assisted etching, galvanic displacement, topochemical and cation exchange reactions are proposed as simple routes to fabricate large scale, vertically aligned CdTe-Si hybrid nanostructures with high density.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.11
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• pp.922-925
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• 2012

Single crystalline Au nanowires were successfully synthesized in a tube-type furnace. The Au nanowires were grown by vapor phase synthesis technique using solid-liquid-solid (SLS) mechanism on substrates of corning glass and Si wafer. Prior to Au nanowire synthesis, Au thin film served as both catalyst and source for Au nanowire was prepared by sputtering process. Average length of the grown Au nanowires was approximately 1 ${\mu}m$ on both the corning glass and Si wafer substrates, while the diameter and the density of which were dependent on the thickness of the Au thin film. To induce a super-saturated states for the Au particle catalyst and Au molecules during the Au nanowire synthesis, thickness of the Au catalyst thin film was fixed to 10 nm or 20 nm. Additionally, synthesis of the Au nanowires was carried out without introducing carrier gas in the tube furnace, and synthesis temperature was varied to investigate the temperature effect on the resulting Au nanowire characteristics.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.115-115
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• 2003

Silica nanostructures have been attached considerable attention because of theirs potential application in mesoscopic research and the potential use of large surface area structure of catalysts. SiO2 nannowire and nanorods was synthesized various methods including thermal evaporation, chemical vapor deposition (CVD), and laser ablation methods. In this experiments, SiO2 nanowire were grown using thermal evaporation method followed by VS (Vapor-Solid) growth mechanisms. Grown SiO2 nanowires were amorphous phases because of its low growth temperatures. Grown nanowires diameters were about 20-40nm at all growth conditions, but its microstructres were different by that used substrate because of it's oxygen contents.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.2
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• pp.66-69
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• 2003

Various semiconductor nanowires such as GaN, GaP, InP, Si$_3$N$_4$, SiO$_2$/Si, and SiC were coated conformally with aluminum oxide (Al$_2$O$_3$) layers by atomic layer deposition (ALD) using trimethylaluminum (TMA) and distilled water ($H_2O$) at a temperature of 20$0^{\circ}C$. Transmission electron microscopy (TEM) revealed that A1203 cylindrical shells conformally coat the semiconductor nanowires. This study suggests that the ALD of $Al_2$O$_3$ on nanowires is a promising method for preparing cylindrical dielectric shells for coaxially gated nanowire field-effect transistors.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.357-361
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• 2016

Si와 InAs 두 가지 채널 물질을 가지고 3가지 수송 방향 <100>, <110>, <111>으로 변화시키며 각각의 Nanowire nMOSFETs을 가지고 ballistic quantum transport simulation을 진행하였다. 각각의 경우에 대해 E-k curve를 구한 다음에 band curvature로 캐리어의 유효질량을 계산하고, 이를 통해 MOSFET의 전류 세기를 결정짓는 DOS와 carrier injection velocity를 구하여 어떤 경우에 가장 높은 ON-current를 흐르게 하는지 확인해 보았다. 하지만 예상과 달리 나노와이어의 직경이 1.4nm으로 매우 작기 때문에 valley-splitting이 일어나 Si<110>의 경우에 가장 작은 캐리어 유효 질량을 갖고 있는 사실을 확인할 수 있었다. 결론적으로 Si<100>의 경우에 trade-off 관계에 있는 DOS와 carrier injection velocity가 6가지 경우 중 최적의 조합을 가짐으로써 가장 높은 ON-current를 흐르게 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.413-413
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• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.

• Korean Journal of Materials Research
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• v.24 no.10
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• pp.509-514
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• 2014

We demonstrate a simple and effective method to accurately position silicon nanowires (Si NWs) at desirable locations using drop-casting of Si NW inks; this process is suitable for applications in nanoelectronics or nanophotonics. Si NWs were assembled into a lithographically patterned sacrificial photoresist (PR) template by means of capillary interactions at the solution interface. In this process, we varied the type of solvent of the SiNW-containing solution to investigate different assembly behaviors of Si NWs in different solvents. It was found that the assembly of Si NWs was strongly dependent on the surface energy of the solvents, which leads to different evaporation modes of the Si NW solution. After Si NW assembly, the PR template was cleanly removed by thermal decomposition or chemical dissolution and the Si NWs were transferred onto the underlying substrate, preserving its position without any damage. This method enables the precise control necessary to produce highly integrated NW assemblies on all length scales since assembly template is easily fabricated with top-down lithography and removed in a simple process after bottom-up drop-casting of NWs.