• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.501-504
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• 2014

Si nanowire는 트랜지스터, 배터리 등 광범위한 응용이 가능한 물질로서 이의 효율적 활용을 위해서는 그 다양한 구조에 대한 물성 변화의 연구가 중요하다. 이 연구에서는 [110] 방향의 $4{\times}3$, $6{\times}4$, $8{\times}5$ Si nanowire에 대하여 DFT 기반 제일원리적 계산을 수행함으로써, $6{\sim}14{\AA}$ 범위에서 nanowire 지름의 변화에 따른 전자구조 의존성에 대하여 연구하였다. 그 결과, bulk와 비교하여 Si nanowire의 경우 bandwidth 감소 및 bandgap의 증가가 나타나며, 이러한 경향은 nanowire 지름이 커질수록 점진적으로 약화됨을 알 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.91-95
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• 2012

ZnO thin films were deposited on p-type 4H-SiC substrate by pulsed laser deposition. ZnO nanowires were formed on p-type 4H-SiC substrate by furnace. Ti/Au electrodes were deposited on ZnO thin film/SiC and ZnO nanowire/SiC structures, respectively. Structural and crystallographical properties of the fabricated ZnO thin film/SiC and ZnO nanowire/SiC structures were investigated by field emission scanning electron microscope and X-ray diffraction. In this work, resistance and sensitivity of ZnO thin film/SiC gas sensor and ZnO nanowire/SiC gas sensor were measured at $300^{\circ}C$ with various CO gas concentrations (0%, 90%, 70%, and 50%). Resistance of gas sensor decreases at CO gas atmosphere. Sensitivity of ZnO nanowire/SiC gas sensor is twice as big as sensitivity of ZnO thin film/SiC gas sensor.

• Korean Journal of Materials Research
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• v.20 no.1
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• pp.25-30
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• 2010

Si nanowire/multiwalled carbon nanotube nanocomposite arrays were synthesized. Vertically aligned Si nanowire arrays were fabricated by Ag nanodendrite-assisted wet chemical etching of n-type wafers using $HF/AgNO_3$ solution. The composite structure was synthesized by formation of a sheath of carbon multilayers on a Si nanowire template surface through a thermal CVD process under various conditions. The results of Raman spectroscopy, scanning electron microscopy, and high resolution transmission electron microcopy demonstrate that the obtained nanocomposite has a Si nanowire core/carbon nanotube shell structure. The remarkable feature of the proposed method is that the vertically aligned Si nanowire was encapsulated with a multiwalled carbon nanotube without metal catalysts, which is important for nanodevice fabrication. It can be expected that the introduction of Si nanowires into multiwalled carbon nanotubes may significantly alter their electronic and mechanical properties, and may even result in some unexpected material properties. The proposed method possesses great potential for fabricating other semiconductor/CNT nanocomposites.

• Korean Journal of Materials Research
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• v.13 no.10
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• pp.677-682
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• 2003

SiC nanowires were synthesized by carbothermal reduction using metal catalysts. Synthesized nanowires had mean diameters of 30∼50 nm and several $\mu\textrm{m}$ length. The kind of catalysts affects form of SiC nanowire because of difference of growth mechanisms. These differences were made by catalyst's physical property and relative activities to the source gas. Ni acted a conventional catalyst of VLS growth mechanism. But, Case of Fe, SiC nanowire was grown by stable VLS growth mechanism without relation of growth conditions. SiC nanowire was grown by two step growth model using Cr catalyst. Conversion ratios to the SiC nanowire were increased with growth conditions. Case of Cr, conversion ratio was about 45% that was higher than other catalyst used. This high conversion ratio was obtained by the addition VS growth to radial direction on the as-grown nanowires.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.303.1-303.1
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• 2014

좋은 전기적 특성을 가지면서 소자의 크기를 줄이기에 용이한 Gate-all-around (GAA) twin Si nanowire field-effect transistors (TSNWFETs)의 연구가 많이 진행되고 있다. Switching 특성과 단채널 효과가 없는 TSNWFETs의 특성은 GAA 구조의 본질적인 특성이다. TSNWFETs는 기존의 single Si nanowire TSNWFETs와 bulk FET에 비하여 Drive current가 nanowire의 지름에 많은 영향을 받지 않는다. 그러나 TSNWFETs의 전체 on-current는 훨씬 작고 nanowire의 지름이 작아지면서 줄어들게 되면서 소자의 sensing speed와 sensing margin 특성의 악화를 가지고 온다. GAA TSNWFETs의 제작 및 전기적 실험에 대한 연구는 많이 진행되었으나, GAA TSNWFETs의 전기적 특성에 대한 이론적 연구는 매우 적다. 본 연구에서는 GAA TSNWFETs의 nanowire 크기에 따른 전기적 특성을 관찰하였다. GAA TSNWFETs와 bulk FET의 전기적 특성을 양자역학을 고려하여 3차원 TCAD 시뮬레이션을 툴을 이용하여 계산하였다. GAA TSNWFETs와 bulk FET의 전류-전압 특성 계산을 통해 on-current 크기, subthreshold swing, drain-induced barrier lowering (DIBL), gate-induced drain leakage를 보았다. 전류가 흐르는 경로와 전기적 특성의 물리적 의미에 대한 연구를 위해 TSNWFETs에서의 전류 밀도, conduction band edge, potential 특성을 분석하였다. 시뮬레이션 결과를 통해 Switching 특성, 단채널 효과에 대한 면역 특성, nanowire의 단면적에 따른 전류 흐름을 보았다. nanowire의 크기가 작아지면서 DIBL이 증가하고 문턱전압과 전체 on-current는 감소하면서 소자의 특성이 악화된다. 이러한 결과는 GAA TSNWFETs의 전기적 특성을 이해하고 좋은 소자 특성을 위한 구조를 연구하는데 많은 도움이 될 것이다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.125.2-125.2
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• 2016

Semiconductor nanowires are essential building blocks for various nanotechnologies including energy conversion, optoelectronics, and thermoelectric devices. Bottom-up synthetic approach utilizing metal catalyst and vapor phase precursor molecules (i.e., vapor - liquid - solid (VLS) method) is widely employed to grow semiconductor nanowires. Al has received attention as growth catalyst since it is free from contamination issue of Si nanowire leading to the deterioration of electrical properties. Al-catalyzed Si nanowire growth, however, unlike Au-Si system, has relatively narrow window for stable growth, showing highly tapered sidewall structure at high temperature condition. Although surface chemistry is generally known for its role on the crystal growth, it is still unclear how surface adsorbates such as hydrogen atoms and the nanowire sidewall morphology interrelate in VLS growth. Here, we use real-time in situ infrared spectroscopy to confirm the presence of surface hydrogen atoms chemisorbed on Si nanowire sidewalls grown from Al catalyst and demonstrate they are necessary to prevent unwanted tapering of nanowire. We analyze the surface coverage of hydrogen atoms quantitatively via comparison of Si-H vibration modes measured during growth with those obtained from postgrowth measurement. Our findings suggest that the surface adsorbed hydrogen plays a critical role in preventing nanowire sidewall tapering and provide new insights for the role of surface chemistry in VLS growth.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.1
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• pp.128-133
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• 2013

Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.6
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• pp.256-259
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• 2006

The amorphous $SiO_x$ nanowires were synthesized by the vapor phase epitaxy (VPE) method. $SiO_x$ nanowires were formed on silicon wafer of temperatures ranged from $800{\sim}1100^{\circ}C$ and nickel thin film was used as a catalyst for the growth of nanowires. A vapor-liquid-solid (VLS) mechanism is responsible for the catalyst-assisted amorphous $SiO_x$ nanowires synthesis in this experiment. The SEM images showed cotton-like nanostructure of free standing $SiO_x$ nanowires with the length of more than about $10{\mu}m$. The $SiO_x$ nanowires were confirmed amorphous structure by TEM analysis and EDX spectrum reveals that the nanowires consist of Si and O.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.101-105
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• 2006

Nanoscale floating-gate characteristic of colloidal Au nanoparticles electrostatically assembled on the oxidized surface of Si nanowires have been investigated. The Si nanowire split-gate transistor structure was fabricated by electron beam lithography and subsequent reactive ion etching. Colloidal Au nanoparticles with ${\sim}5$ nm diameters were selectively deposited onto the Si nanowire surface by 2 min electrophoresis. It was found that electric fields applied to the self-aligned split side gates allowed charge to be transferred on the Au nanoparticles. It was observed that the depletion mode cutoff voltage, induced by the self-aligned side gates, was shifted by more than 1 V after Au nanoparticle electrophoresis. This may be due to the semi-one dimensional nature of the narrow Si nanowire transport channel, having much enhanced sensitivity to charges on the surface.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.