• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.160-167
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• 2003

A static shuffle-exchange network is not only useful for several parallel applications but also use less hardware than the popular multi-stage network or hypercube. Even though it has a lot of advantages, it has never been used in any implemented parallel machine. One of the reasons is there has not been any techniques to make the network fault-tolerant. In this paper multiple fault-tolerant static shuffle-exchange networks are presented. In order to recover from k faulty processing elements, a network needs at least 2 k additional processing elements and at most 4 k additional shuffle ports for each processing elements. By decomposing the k fault-tolerant static shuffle-exchange network into m identical modules, this paper shows that the reliability of the network can be increased.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.130-137
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• 2003

This paper presents the problem of partitioning the Single-Stage Shuffle-Exchange Network(SSEN). An algorithm, named SSEN_to_PSEN, is devised to transform an SSEN into a Partitionable Shuffle-Exchange Network (PSEN). The proposed algorithm presents that the SSEN can be partitioned into independent sub-networks without additional links for N $\leq$ 8. Additional links are needed in order to partition an SSEN, but only when N $\geq$ 16. The running time of the algorithm SSEN_to_PSEN is $\theta$(NlogN). By comparing with a hypercube network, the PSEN is less expensive than a hypercube network even when some additional links are added. By partitioning, a large PSEN in a massively parallel machine can compute various problems for multiple users simultaneously, thereby the processing efficiency of the machine is improved.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.217-224
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• 1986

In case of VLSI design, the shuffle-exchange graph is useful for optimal layout. HOEY and LEISERSON proposed the method of drawing a N-nodes shuffle-exchange graph on O(N2/log N) layout area by using the complex plane digram. [2] In this paper, a new algorithm for drawing the shuffle-exchange graph is proposed. This algorithm is not by using the complex plane diabram, but the table of e decimal represented nodes of shuffle-edge relations. And the structural properties for optimal layout of the graph are summarized and verified. By using this more simplified algorithm, a FORTRAN program which can be treated faster is written. Aimed near optimal shuffle-exchange graphs are printed out by giving inputs` the number of nodes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.355-361
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• 1987

The shuffle-exchange graph is known as a structure to perform the parallel algorithms like Discrete Fourier Transform(DFT), matrix multiplication and sorting. In this paper, the layout for the shuffle-exchange graph is described and this layout places emphasis on the placement of nodes that has the capability to have as small area as possible, have as a small number of crossings as possible, and have as short wires as possible. The algorithm corrdsponding these conditions is proposed and each evaluation factor and the placement of the N-node shuffle-exchange graph is performed with FORTRAN and BASIC program, and these results are calcualted.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1842-1850
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• 1997

This paper proposes a new rearrangeable algorithm in multistage reverse shuffle/exchange network. The best known lower bound of stages for rearrangeability in symmetric network is 2logN-1 stages. However, it has never been proved for nonsymmetric networks before. Currently, the best upper bound for the rearrangeability of a shuffle/exchange network in nonsymmetric network is 3logN-3 stages. We describe the rearrangeability of reverse shuffle/exchange multistage interconnection network on every arbitrary permutation with $N{\le}16$. This rearrangeability can be established by setting one more stages in the middle stage of the network to allow the reduced network to be topological equivalent to a class of rearrangeable networks. The results in this paper enable us to establish an upper bound, 2logN stages for rearrangeable reverse shuffle/exchange network with $N{\le}16$, and leads to the possibility of this bound when $N{\le}16$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10B
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• pp.1807-1814
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• 1999

This paper considers connectivity-related reliability measures for a class of fault-tolerant shuffle exchange networks to characterize the degrading features over time in the presence of faulty switching elements. The mean number of connected input/output pairs, the mean number of survivable input are considered as connectivity measures. The measures for the unique-path shuffle exchange network(SEN) and its two fault-tolerant variants, extra-stage SEN(SEN+) and INDRA network are derived analytically, and then are compared with numerical experiments.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1949-1955
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• 2000

This paper proposes a multistage interconnection ATM switching network without internal blocking. The first is recirculating shuffle-exchange network improved on hardware complexity. The next is connected to Rank network with tree structure. In this network, after the packets transferred to the same output ports are given each priority, only a packet with highest priority is sent to the next, an the others are recirculated to the first. Rearrangeability through decomposition and composition algorithm is applied for the transferred packets in hanyan network and all they arrive at a final destinations. To analyze throughput, waiting time and packet loss ratio according tothe size of buffer, the probabilities are modeled by a binomial distribution of packet arrival.

• The Journal of the Korea Contents Association
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• v.4 no.4
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• pp.189-196
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• 2004

Most of the recent researches for ATM switches have been based on multistage interconnection network known as regularity and self-routing property. These networks can switch packets simultaneously and in parallel. However, they are blocking networks in the sense that packet is capable of collision with each other Mainly Banyan network have been used for structure. There are several ways to reduce the blocking or to increase the throughput of banyan-type switches: increasing the internal link speeds, placing buffers in each switching node, using multiple path, distributing the load evenly in front of the banyan network and so on. Therefore, this paper proposes the use of recirculating shuffle-exchange network to reduce the blocking and to improve hardware complexity. This structures are recirculating shuffle-exchange network as simplified in hardware complexity and Rank network with tree structure which send only a packet with highest priority to the next network, and recirculate the others to the previous network. after it decides priority number on the Packets transferred to the same destination, The transferred Packets into banyan network use the function of self routing through decomposition and composition algorithm and all they arrive at final destinations. To analyze throughput, waiting time and packet loss ratio according to the size of buffer, the probabilities are modeled by a binomial distribution of packet arrival. If it is 50 percentage of load, the size of buffer is more than 15. It means the acceptable packet loss ratio. Therefore, this paper simplify the hardware complexity as use of recirculating shuffle-exchange network instead of bitonic sorter.

• Proceedings of the Korea Multimedia Society Conference
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• 1998.04a
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• pp.366-370
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• 1998

One major limitation of the efficiency of parallel computer designs has been the prohibitively high cost of parallel communication between processors and memories. Linear order concentrators can be used to build theoretically optimal interconnection schemes. Current designs call for building superconcentrators from concentrators, then using these to recursively partition the connection streams O(log2N) times to achieve point-to-point routing. Since the superconcentrators each have O(N) hardware complexity but O(log2N) depth, the resulting networks are optimal in hardware, but they are of O(log2N) depth. This pepth is not better than the O(log2N) depth Bitonic sorting networks, which can be implemented on the O(N) shuffle-exchange network with message passing. This paper introduces a new method of constructing networks using linear order concentrators and expanders, which can be used to build interconnection networks with O(log2N) depth as well as O(Nlog2N) hardware cost. (All logarithms are in base 2 throughout paper)

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.173-178
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• 1999

The Trellis Coded Modulation(TCM) allows the considerable achievements of coding gains compare with conventional multi-level modulation without compromising bandwidth efficiency. In this paper, we are presented a design of the parallel Viterbi decoder for 16-QAM TCM decoder with large constraint length (K=9), which can be applicable for the Digital Audio Broadcasting(DAB) receiver. As a mid-term result, a parallel Branch Metric Calculator (BMC)can compute 16 BMs within 3 clocks and a parallel 16 Add-Compare-Selects (ACS) unit can compute in a single clock. And also, two 256 Path Metric Memories (PMM) 32 Trace Back(TB) memories are specially designed with shuffle exchange switches for 16 parallel accesses. As a VHDL simulation, we can find the correctness of proposed model, which can be operated 16 S per symbol. Now, we are performing the hardware reduction for realtime operation and FPGA implementation.