• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2008년도 International Symposium on Remote Sensing
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• pp.426-429
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• 2008

In this study, we propose the calibration algorithm for the solar channel (550 ${\sim}$ 900 nm) of MTSAT 1R which is the Japanese geostationary satellite launched on 26 Feb. 2005 and located at $140^{\circ}E$. We developed a method utilizing MODIS-derived BRDFs for the solar channel calibration over the bright desert area. Targets are selected based on the desert's brightness, spatial uniformity, temporal stability and spectral stability. The 6S model has been incorporated to account for directional effects of the surface using MODIS-derived BRDF parameters within the spectral interval in interest. Results based on the analysis for the period from November 2007 to June 2008 suggest that MTSAT-1R solar channel measurements have a low bias within 5%.

• 전자공학회논문지A
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• 제30A권12호
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• Journal of information and communication convergence engineering
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• 제8권1호
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.107-116
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• 1994

In the manufacturing of VLSI circuits, variations of device characteristics due to the slight differences in process parameters drastically aggravate the performances of fabricated devices. Therefore, it is very important to establish optimal process conditions in order to minimize deviations of device characteristics. In this paper, we used one-dimensional process simulator, SUPREM-II, and two dimensional device simulator, MINIMOS 4.0 in order to extract optimal process parameter which can minimize changes of the device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derived the dependence relations between process parameters and device characteristics. Here, we have suggested a method to extract process parameters from design trend curve(DTC) obtained by these dependence relations. And we have discussed short channel effects and device limitations by scaling down MOSFET dimensions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.225-230
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• 1994

In this paper, we have fabricated short channel MOSFETs with these parameters to verify the validity of process parameters extraction by DTC method. The experimental results of fabricated short channel devices according to the optimal process parameters demonstrate good device characteristics such as good drain current-voltage characteristics, low body effects and threshold voltage of$\leq$+-.1.0V, high punch through and breakdown voltage of$\leq$12V, low subthreshold swing(S.S) values of$\leq$105mV/decade.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.555-558
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• 2006

블루투스는 전자기기 사이의 연결성을 위한 근거리 무선통신 기술의 표준이다. 본 논문은 블루투스 시스템에서 동일채널간섭의 영향을 분석하였고 수신된 비트의 BER과 SIR을 기반으로 성능을 평가하였다. 다양한 채널상태를 나타내기 위하여 Eb/No와 SIR 값에 따라서 블루투스 시스템의 성능을 분석하여 결과 그래프에 나타내었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• The Korean Journal of Pain
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• 제24권2호
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• pp.74-80
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• 2011

Background: Lidocaine patch (L5P) has demonstrated short-term efficacy in treating both acute surgical pain and chronic neuropathic pain with tolerable side effects. Percutaneous endoscopic lumbar discectomy (PELD) is the mainstay of minimally invasive spine surgery (MISS). Sufficient analgesia during PELD surgery makes the patient consider it real MISS. This study was performed to evaluate the efficacy and adverse effects of lidocaine patch in patients who underwent PELD under local anesthesia. Methods: L5P (L group) or placebo (P group) was randomly applied on the skin of the back covering the anticipated path of the working channel before 1 hour of surgery in 100 patients who underwent a single level PELD at L4-L5. Efficacy of the lidocaine patch was assessed by patient's numeric rating scale (NRS) of pain at each stage during the surgery and by a 5-scale grading of the satisfaction with the anesthesia of the operator and patients after surgery. Results: Mean NRS scores at the stages of needle insertion, skin incision, serial dilation and insertion of working channel, and subcutaneous suture were significantly lower in the L group than the P group. Postoperative operator's and patients' satisfaction scores were also significantly higher in L group than in the P group. There were subtle adverse effects in both groups. Conclusions: L5P provided better pain relief during PELD, especially at the stage of needle insertion, skin incision, serial dilation and insertion of working channel, and subcutaneous suture. It also provided higher patient and operator postoperative satisfaction, with only subtle adverse effects.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 추계학술대회
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• pp.715-717
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• 2010

본 연구에서는 MicroTec4.0을 이용하여 더블게이트 MOSFET의 문턱전압이하특성을 채널도핑농도의 변화에 따라 분석하였다. DGMOSFET는 구조상 단채널효과를 감소시킬 수 있다는 장점 때문에 많은 연구가 진행중에 있다. 이에 DGMOSFET에서 단채널효과로서 잘 알여진 문턱전압이하 스윙 및 문턱전압 등을 반도체소자 시뮬레이이터인 MicroTec을 이용하여 분석하고자 한다. 나노소자인 DGMOSFET의 구조적 특성도 함께 고찰하기 위하여 채널의 두께, 길이, 폭 등 크기요소에 따라 분석하였다. 본 논문에서 사용한 MicroTec 프로그램은 여러 논문에서 수치해석학적 값과 비교하여 그 타당성이 입증되었으므로 이 모델을 이용하여 DGMOSFET의 문턱전압이하특성을 분석하였다.