• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2183-2188
• /
• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.05a
• /
• pp.748-751
• /
• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.3
• /
• pp.139-142
• /
• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.51 no.3
• /
• pp.134-140
• /
• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• Biomolecules & Therapeutics
• /
• v.18 no.4
• /
• pp.448-453
• /
• 2010

Drug-induced long QT syndrome is known to be associated with the onset of torsades de pointes (TdP), resulting in a fatal ventricular arrhythmia. QT interval prolongation can result from blocking the human ether-a-go-go-related gene (hERG) channel, which is important for the repolarization of cardiac action potential. Nicardipine, a Ca-channel blocker and antihypertensive agent, has been reported to increase the risk of occasional serious ventricular arrhythmias. We studied the effects of nicardipine on hERG $K^+$ channels expressed in HEK293 cells and Xenopus oocytes. The cardiac electrophysiological effect of nicardipine was also investigated in this study. Our results revealed that nicardipine dose-dependently decreased the tail current of the hERG channel expressed in HEK293 cells with an $IC_{50}$ of 0.43 ${\mu}M$. On the other hand, nicardipine did not affect hERG channel trafficking. Taken together, nicardipine inhibits the hERG channel by the mechanism of short-term channel blocking. Two S6 domain mutations, Y652A and F656A, partially attenuated (Y652A) or abolished (F656A) the hERG current blockade, suggesting that nicardipine blocks the hERG channel at the pore of the channel.

• Journal of Electrical Engineering and Technology
• /
• v.3 no.4
• /
• pp.566-570
• /
• 2008

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.317-320
• /
• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.22 no.1
• /
• pp.34-49
• /
• 1998

In this study, turbulent flows in a grooved channel are numerically investigated by Large Eddy Simulation (LES). Especially, a parametric study is carried out to study effects of length and depth of a groove on large-scale flow structures. For one test case, comparison of LES results with those of DNS reveals a good agreement even though the number of grid points of LES is only 6.5% of that of DNS. This confirms that LES is a suitable tool for a parametric study of turbulent flows. The subsequent parametric study using LES shows that the large-scale turbulent structures are significantly affected by the geometry of the groove. Especially, when the length of the groove is short such that the recirculation region occupies the entire groove, the turbulent flow in the groove becomes very weak in both mean and fluctuation quantities.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.3
• /
• pp.233-237
• /
• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.1
• /
• pp.92-97
• /
• 2008

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.