• ETRI Journal
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• 제36권1호
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• 대한전자공학회논문지
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• 제27권9호
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.84-84
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• 2010

In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Journal of information and communication convergence engineering
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• 제21권2호
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• pp.103-109
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• 2023

We investigated the antipodal-symmetric dispersion maps of a dispersion-managed link with a midway optical phase conjugator to compensate for the distorted 960 Gb/s wavelength division multiplexed (WDM) signal caused by these effects. The proposed antipodal-symmetric dispersion map has various shapes depending on the detailed design scheme. We confirmed that the dispersion-managed link designed with the dispersion map of the antipodal-symmetric structure is more advantageous than the conventional uniform dispersion map for compensating WDM channels. It was also confirmed that among the antipodal-symmetric structures, the dispersion map configured with the S-1-profile, in which S is inverted up and down, was more effective for distortion compensation than the dispersion map configured with the S-profile. In particular, we confirmed that the S-1-profile can broaden the optical pulse width intensively at a short transmission distance, more effectively compensating for the distorted WDM channel. Because this structure makes the intensity of the optical pulse relatively weak, it can decrease the nonlinear Kerr effect.

• 한국전기전자재료학회논문지
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• 제25권2호
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• pp.100-104
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• 2012

Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.

• 정보처리학회논문지C
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• 제13C권7호
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• pp.803-812
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• 2006

본 논문에서는 저속의 무선 센서 네트워크(WSN: Wireless Sensor Network)에서 블록 FEC(Forward Error Correction) 알고리즘의 심볼 크기의 변화에 따른 802.11 MAC 프로토콜의 전송 효율과 전송 에너지를 해석적으로 분석한다. 블록 FEC 알고리즘은 심볼(symbol) 단위로 오류를 복원하므로, 주어진 무선 센서 채널에서 같은 FEC 체크 비트(check bit) 량을 사용하더라도 블록 FEC 알고리즘의 오류 패킷 복원률은 블록 FEC 심볼 크기에 의존적이다. 즉, 같은 양의 FEC 체크 비트를 사용하는 경우에, 연속된 군집 오류 길이는 작으면서 군집 오류가 자주 발생하는 채널에서는 작은 FEC 심볼이, 이에 반해 군집 오류의 길이는 크고 군집 오류 개수가 작은 군집적 분포를 보이는 채널에서 큰 FEC 심볼이 효율적이다. 심볼 크기의 영향을 평가하기 위해서 본 논문에서는 센서 노드 TIP50CM을 사용하는 WSN에서 수집한 패킷 트레이스를 기반으로 WSN 채널을 Gilbert 모델로 모델링하고, 심볼 크기가 다른 RS(Reed-Solomon) 코드를 생성하고 해석하기 위한 에너지를 측정하였다. 이러한 모델링된 채널과 각 RS 코드 생성과 해석 에너지를 이용하여 FEC 심볼 크기에 따른 RS FEC 코드를 채택한 802.11 MAC 프로토콜의 전송 효율과 전송 에너지를 계산하였다. 실제 측정 데이터와 해석적으로 계산한 데이터를 결합한 계산에 의하면 비슷한 FEC 체크 비트 량을 사용하더라도 FEC 심볼 크기에 따라 전송 효율은 최대 4.2%, 그리고 소요 에너지는 최대 35%의 차이가 발생한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.294.1-294.1
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• 2016

Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3. The doping level is controlled in the non-degenerate regime, where performance parameters of PPh3 doped WSe2 transistor can be optimized.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• 한국유통학회지:유통연구
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• 제16권3호
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• pp.105-133
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• 2011

본 연구는 친환경농산물 구매에 있어서 소비자들이 생각하는 가격변수의 중요도를 살펴보고 가격수준에 대한 소비자의 의견에 영향을 미치는 요인들을 분석하는데 그 목적이 있다. 연구의 결과를 보면, 직접질문 결과 현재 친환경농산물 구매에 있어서 소비자들은 '제품에 대한 상세한 설명', '유통채널', '친환경식품 표기에 대한 신뢰' 등을 가격보다 더 중요하게 생각하고 있는 것으로 나타났다. 다음으로 서열로짓분석 결과가 제시하는 바는 '어린 자녀의 수'나 '가족 중 환자 유무' 등 상황적 요인이 친환경농산물의 가격수준에 대한 소비자들의 의견에 가장 큰 영향을 미치는 변수로 나타났다. 그리고 마지막으로 컨조인트분석 결과를 보면 '유통채널'이 가장 중요한 속성으로 나타났으며, 다음으로 '표기에 대한 신뢰' 그리고 가격 순으로 나타났다. 이는 첫 번째 직접질문방식의 결과가 제시하는 바와 비슷한 결과로 풀이된다. 즉 '친절한 설명'이라는 변수는 컨조인트분석에 포함하지 않았음을 감안할 때, 주어진 상품프로파일 상의 선택을 이용한 간접적인 분석 결과와 직접적으로 질문한 결과가 같은 의미를 제공하고 있음을 알 수 있다.