• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• Progress in Superconductivity
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• v.3 no.1
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• pp.83-86
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• 2001

We have fabricated a single flux quantum 4-stage shift register with interface-controlled $Y_1$$Ba_2$$Cu_3$$O_{7-x}$(YBCO) Josephson junction. The YBCO Josephson junctions showed RSJ-like current-voltage(I-V) curves at temperatures 45~80K. We tested load and shift operation of shift register with binary data sequences “1000”, “1010”, “1011”, and “1111” at 58K. For all the binary data sequences, the shift register operated successfully. By operating the circuit with proper current pulses, we observed no errors during at least 12 hours operation for all the data sequences.s.

• Journal of Mechanical Science and Technology
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• v.16 no.7
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• pp.882-888
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• 2002

In this paper, an algorithm to increase the shift speed is suggested by increasing the line pressure for a metal belt CVT. In order to control the shift speed, an algorithm to calculate the target shift speed is presented from the modified CVT shift dynamics. In applying the shift speed control algorithm, a criterion is proposed to prevent the excessive hydraulic loss due to the increased line pressure. Simulations are performed based on the dynamic models of the hydraulic control valves, powertrain and the vehicle. It is found from the simulation results that performance of the engine operation can be improved by the faster shift speed, which results in the improved fuel economy by 2% compared with that of the conventional electronic control CVT in spite of the increased hydraulic loss due to the increased line pressure.

• Proceedings of the KSME Conference
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• 2001.06b
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• pp.546-551
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• 2001

In this paper, an algorithm to improve the optimal engine operation is suggested by increasing the CVT shift speed. By rearranging the CVT shift dynamic equation, it is found that the CVT shift speed depends on the line pressure as well as the primary pressure. Based on the shift dynamics, an algorithm to accomplish a faster shift speed is presented by increasing the line pressure. In order to apply the algorithm, dynamic models of the line pressure control valve and the ratio control valve are obtained by considering the CVT shift dynamics and model based controllers are designed. It is found from the simulation results that fuel economy can be improved by 2% in spite of the increased hydraulic loss due to the increased line pressure.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.8
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• pp.20-29
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• 2011

This paper presents an improved phase-shift pulse-width modulation (PWM) full-bridge converter using a blocking capacitor. As the proposed converter reduces the circulation energy by inserting only one series blocking capacitor at the primary side of the conventional phase-shift PWM full-bridge converter structure, it improves the operation characteristics of the conventional converter. In this paper, first, the operation of conventional phase-shift PWM full-bridge converter is roughly reviewed, and then the operational principle of the proposed converter is classified and explained by each mode. After that, a prototype design example based on the operational principle is shown. Then, the improved operation characteristics of the proposed converter are actually verified through the experimental results.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.10
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• pp.855-859
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• 2007

Hydrogen as an energy carrier in fuel cell offers perhaps the largest potential benefits of reduced emissions of pollutants and greenhouse gases. The generation of high-purity hydrogen from hydrocarbon fuels is essential for efficient operation of fuel cell. Reduction of carbon monoxide to an acceptable level of 10ppm involves high temperature and low temperature water gas shift (WGS), followed by selective oxidation of residual carbon monoxide. The WGS reactor was designed and tested in this study to produce hydrogen-rich gas with CO to less than 5000 ppm. In the water gas shift operation, gas emerges from the reformer is taken through a high temperature shift (HTS) catalyst to reduce the CO concentration to about $2{\sim}4%$ followed to about 5000 ppm via a low temperature shift (LTS) catalyst.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.636-644
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• 2015

This research aims to suggest methods to improve object tracking performance by combining CAM shift algorithm with 8-way search window, and reduce arithmetic operation by reducing the number of frame used for tracking. CAM shift has its adverse effect in tracking methods using signature color or having difficulty in tracking rapidly moving object. To resolve this, moving search window of CAM shift makes it possible to more accurately track high-speed moving object after finding object by conducting 8-way search by using information at a final successful timing point from a timing point missing tracking object. Moreover, hardware development led to increased unnecessary arithmetic operation by increasing the number of frame produced per second, which indicates efficiency can be enhanced by reducing the number of frame used in tracking to reduce unnecessary arithmetic operation.

• Progress in Superconductivity
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• v.1 no.2
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• pp.105-109
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• 2000

We have designed and fabricated a single-flux-quantum(SFQ) four-stage shift register using YBCO bicrystal Josephson junctions, and tested its operations using a digital measurement set-up. The circuit consists of 4 shift register stages and a read SQUID placed next to each side of the shift register. Each SQUID was inductively coupled to the nearby shift register stage. The major obstacle in testing the circuits was the interference between the two read SQUIDs, and we could get over the problem by determining the correct operation points of the SQUID from the simultaneously measured modulation curves. Loaded data ('1' or '0') were successfully shifted from a stage to the next by a controlled current pulse injected to the bias lines located between the stages, and the corresponding correct data shifts were observed with the two read SQUIDs.