• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.46-55
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• 2014

PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8dB improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• The Journal of the Acoustical Society of Korea
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• v.24 no.7
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• pp.387-394
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• 2005

In this paper, we propose a new transmission technique of audio signals for the serial connection of the speakers of multiple-channel audio systems. Analog audio signals from a multi-channel audio system are converted into digital signals with signal processing steps and transferred to each speaker through a serial line. The signal processing steps contain data compression and packet generation in association with audio signal characteristics. Each speaker gets its corresponding digital audio signals from the transmitted packets and converts the signals into analog audio signals to make sounds with the speaker All the proposed functions in this paper are modeled in VHDL. implemented with FPGA chips, and tested for actual multi-channel audio systems.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.62-65
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• 1998

This paper presents a method and implementation of the parallel distributed sample scrambler(DSS) in the cell-based ATM transmission environment. In the serial processing, it requires very high speed clock because the processing clock of the serial DSS is equal with the data transmission speed. In this paper, we develop a conversion method of the serial SRG(shift register generator) to 8bit parallel realization. In this case, it has a sample data processing problem which is a character of DSS. So, a theory of correction time movement is presented to solve this problem. We has developed a ASIC using this algorithm and verified the recommendation of ITU-T, I.432.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5401-5421
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• 2016

Both low-density parity-check (LDPC) codes and the multiple access technique of spatially coupling data transmission (SCDT) can be expressed in bipartite graphs. To improve the performance of iterative demodulation and decoding for SCDT, a novel joint sparse graph (JSG) with SCDT and LDPC codes is constructed. Based on the JSG, an approach for iterative joint demodulation and decoding by belief propagation (BP) is presented as an exploration of the flooding schedule, and based on BP, density evolution equations are derived to analyze the performance of the iterative receiver. To accelerate the convergence speed and reduce the complexity of joint demodulation and decoding, a novel serial schedule is proposed. Numerical results show that the joint demodulation and decoding for SCDT based on JSG can significantly improve the system's performance, while roughly half of the iterations can be saved by using the proposed serial schedule.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2971-2973
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• 2000

In this paper, we proposed the implementation of multiple access serial communications with improved transmission control. For serial communications. RS232 protocol is used and the transmitting data and is merged to form data channel. Multiple host access is configures by using the common data channel and ground channel. 8bit data transfer with variable frame size is transferred by using the 16bit host ID. Packet is composed of HEADER, receiver ID. variable length data frame, TAIL and CRC informations. Multiple hosts are allowed to transfer packet with the other hosts through the common communication channel. Byte-stuffing is used to differentiate the transfer rate of PC is performed.

• Journal of Advanced Navigation Technology
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• v.12 no.5
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• pp.464-469
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• 2008

The RS-232C (Unbalanced serial) and RS-485 (balanced serial) are standard in serial communication. RS-485 uses a differential electrical signal, as opposed to unbalanced signals referenced to ground with the RS-232. Differential transmission, which uses two lines each for transmit and receive signal results in greater noise immunity and longer distances as compared to the RS-232C. The greater noise immunity and distance are big advantages in industrial environments. In general, one protocol on one serial interface is very normal application. In this study, we implemented multi protocols on one serial RS-485 interface and examine the performance and result with hanging multi equipments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.683-684
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• 2016

The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.

• Applied Microscopy
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• v.46 no.2
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• pp.100-104
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• 2016

Electron microscopy is currently the only available technique with a spatial resolution sufficient to identify fine neuronal processes and synaptic structures in densely packed neuropil. For large-scale volume reconstruction of neuronal connectivity, serial block-face scanning electron microscopy allows us to acquire thousands of serial images in an automated fashion and reconstruct neural circuits faster by reducing the alignment task. Here we introduce the whole reconstruction procedure of synaptic network in the rat hippocampal CA1 area and discuss technical issues to be resolved for improving image quality and segmentation. Compared to the serial section transmission electron microscopy, serial block-face scanning electron microscopy produced much reliable three-dimensional data sets and accelerated reconstruction by reducing the need of alignment and distortion adjustment. This approach will generate invaluable information on organizational features of our connectomes as well as diverse neurological disorders caused by synaptic impairments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.255-263
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• 2010

In this paper, we present an efficient cooperative transmission scheme for high speed 60GHz WPAN system. In 60GHz, the cooperative transmission with relay is effective scheme because signals are exceedingly attenuated according to the distance and the transmission is impossible when there is no LOS between transmitter and receiver. Moreover, the reliability of signal in destination can be improved by receiving data from a relay as well as a transmitter. However, the overall data rate is reduced because transmission time is more required for relay. To solve this problem, we propose a cooperative transmission scheme with RS-CC serial concatenated codes. In the proposed cooperative transmission scheme, the relay can reduce the transmission data size because the only parity bits of systematic RS code are transmitted after encoding by CC. But the computational complexity is increased at the relay and the destination.