• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.10C
• /
• pp.973-979
• /
• 2002

In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture needs t x m registers for achieving the t times speed. But, we designed the multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.13 no.5
• /
• pp.429-436
• /
• 1988

This paper presents a method of designing a Bit-Serial Reed-Solomon encoder using Berlekamp's Bit-Serial Multiplier Algorithm and the implementation of the (255, 223) Bit-Serial Reed-Solomon encoder using TTL logics. It is shown from these results that this encoder require substanitially less hardware than the convenional Reed-Solomon encoders.

• The KIPS Transactions:PartA
• /
• v.9A no.3
• /
• pp.281-286
• /
• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.6C
• /
• pp.625-631
• /
• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.3B
• /
• pp.355-361
• /
• 2001

유한체(Galois Field) 상에서의 곱셈(multiplication)을 구현하는 방법은 크게 병렬 곱셈기(parallel multiplier)와 직렬 곱셈기(serial multiplier)로 나누어질 수 있는데, 구현시 하드웨어 면적을 작게 차지한다는 장점 때문에 직렬 곱셈기가 널리 사용된다. 하지만 이 직렬 곱셈기를 이용하여 계산을 하기 위해서는 병렬 곱셈기에 비해 많은 시간이 필요하게 된다. 직렬기법과 병렬기법의 결합이 이를 보완할 수 있게 된다. 본 논문에서는 복잡도는 직렬 곱셈기와 큰 차이가 없으면서 연산시간을 줄인 곱셈기*(multiplier)를 제안하였다. 이 곱셈기를 사용하면 복잡도는 크게 늘어나지 않았으면서 유한체 상에서의 곱셈을 하는데 필요한 시간을 줄이는 효과를 얻을 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.10
• /
• pp.23-30
• /
• 2008

Recently, a considerable number of studies have been conducted on pairing based cryptosystems. The efficiency of pairing based cryptosystems depends on finite fields, similar to existing public key cryptosystems. In general, pairing based ctyptosystems are defined over finite fields of chracteristic three, GF($3^m$), based on trinomials. A multiplication in GF($3^m$) is the most dominant operation. This paper proposes a new most significant digit(MSD)-first digit- serial multiplier. The proposed MSD-first digit-serial multiplier has the same area complexity compared to previous multipliers, since the modular reduction step is performed in parallel. And the critical path delay is reduced from 1MUL+(log ${\lceil}n{\rceil}$+1)ADD to 1MUL+(log ${\lceil}n+1{\rceil}$)ADD. Therefore, when the digit size is not $2^k$, the time delay is reduced by one addition.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.140-143
• /
• 2000

소형화와 안전성에서 보다 더 진보된 ECC( Elliptic Curve Cryptography) 암호화 알고리즘의 하드웨어적 구현을 제안한다. Basis는 VLSI 구현에 적합한 standard basis이며 m=193 ECC 승산기 회로를 설계하였다. Bit-Parallel 구조를 바탕으로 Digit-Serial/Bit-Parallel 방법으로 구현하였다. 제안된 구조는 VHDL 및 SYNOPSYS로 검증되었다.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.345-348
• /
• 2002

This paper presents new fast scalar multiplier of elliptic curve cryptosystem that is regarded as next generation public-key crypto processor. For fast operation of scalar multiplication a finite field multiplier is designed with LFSR type of bit serial structure and a finite field inversion operator uses extended binary euclidean algorithm for reducing one multiplying operation on point operation. Also the use of the window non-adjacent form (WNAF) method can reduce addition operation of each other different points.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.45 no.3
• /
• pp.444-450
• /
• 1996

A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). refs., figs., tabs.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.17 no.1
• /
• pp.33-39
• /
• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.