• Title/Summary/Keyword: Serial links

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Stiffness Analysis of a Low-DOF Parallel Manipulator including the Elastic Deformations of Both Joints and Links (ICCAS 2005)

  • Kim, Han-Sung;Shin, Chang-Rok;Kyung, Jin-Ho;Ha, Young-Ho;Yu, Han-Sik;Shim, Poong-Soo
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.631-637
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    • 2005
  • This paper presents a stiffness analysis method for a low-DOF parallel manipulator, which takes into account of elastic deformations of joints and links. A low-DOF parallel manipulator is defined as a spatial parallel manipulator which has less than six degrees of freedom. Differently from the case of a 6-DOF parallel manipulator, the serial chains in a low-DOF parallel manipulator are subject to constraint forces as well as actuation forces. The reaction forces due to actuations and constraints in each limb can be determined by making use of the theory of reciprocal screws. It is shown that the stiffness model of an F-DOF parallel manipulator consists of F springs related to the reciprocal screws of actuations and 6-F springs related to the reciprocal screws of constraints, which connect the moving platform to the fixed base in parallel. The $6{times}6$ stiffness matrix is derived, which is the sum of the stiffness matrices of actuations and constraints. The six spring constants can be precisely determined by modeling the compliance of joints and links in a serial chain as follows; the link can be considered as an Euler beam and the stiffness matrix of rotational or prismatic joint can be modeled as a $6{times}6$ diagonal matrix, where one diagonal element about the rotation axis or along the sliding direction is zero. By summing the elastic deformations in joints and links, the compliance matrix of a serial chain is obtained. Finally, applying the reciprocal screws to the compliance matrix of a serial chain, the compliance values of springs can be determined. As an example of explaining the procedure, the stiffness of the Tricept parallel manipulator has been analyzed.

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Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

  • Lim, Hyun-Wook;Kong, Bai-Sun;Jun, Young-Hyun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.96-100
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    • 2015
  • Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ${\sum}{\Delta}$ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at $10^{-6}$ BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

Development of a Parallel-Serial Robot Arm for Propeller Grinding (프로펠러 연삭작업을 위한 병렬-직렬 로보트 암 개발)

  • Lee, Min Ki;Choi, Byung Oh;Jung, Jong Yoon;Park, Kun Woo
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.2
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    • pp.146-158
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    • 1996
  • This paper develops a robot arm for propeller blade grinding. The grinding work requires a high stiffness robot arm to reduce deformation and vibration which are generated during machining operation. Conventional articulated robots have serial connecting links from the base to the gripper. Thus, they have very weak structure to the stiffness for grinding operation. Stewart Platform is a typical parallel robotic mechanism with very high stiffness but it has small work space and large installation space. This research proposes a new grinding robot arm by combining parallel mechanism with serial mechanism. Therefore, the robot has large range of work space as well as high stiffness. This paper introduces the automatic system for propeller grinding utilizing the robot and the design of proposed robot arm.

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Stiffness Modeling of a Low-DOF Parallel Robot (저자유도 병렬형 로봇의 강성 모델링)

  • Kim, Han-Sung
    • Journal of Institute of Control, Robotics and Systems
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    • v.13 no.4
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    • pp.320-328
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    • 2007
  • This paper presents a stiffness modeling of a low-DOF parallel robot, which takes into account of elastic deformations of joints and links, A low-DOF parallel robot is defined as a spatial parallel robot which has less than six degrees of freedom. Differently from serial chains in a full 6-DOF parallel robot, some of those in a low-DOF parallel robot may be subject to constraint forces as well as actuation forces. The reaction forces due to actuations and constraints in each serial chain can be determined by making use of the theory of reciprocal screws. It is shown that the stiffness of an F-DOF parallel robot can be modeled such that the moving platform is supported by 6 springs related to the reciprocal screws of actuations (F) and constraints (6-F). A general $6{\times}6$ stiffness matrix is derived, which is the sum of the stiffness matrices of actuations and constraints, The compliance of each spring can be precisely determined by modeling the compliance of joints and links in a serial chain as follows; a link is modeled as an Euler beam and the compliance matrix of rotational or prismatic joint is modeled as a $6{\times}6$ diagonal matrix, where one diagonal element about the rotation axis or along the sliding direction is infinite. By summing joint and link compliance matrices with respect to a reference frame and applying unit reciprocal screw to the resulting compliance matrix of a serial chain, the compliance of a spring is determined by the resulting infinitesimal displacement. In order to illustrate this methodology, the stiffness of a Tricept parallel robot has been analyzed. Finally, a numerical example of the optimal design to maximize stiffness in a specified box-shape workspace is presented.

A Novel 3-Level Transceiver using Multi Phase Modulation for High Bandwidth

  • Jung, Dae-Hee;Park, Jung-Hwan;Kim, Chan-Kyung;Kim, Chang-Hyun;Kim, Suki
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.791-794
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    • 2003
  • The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

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A 5.4Gb/s Clock and Data Recovery Circuit for Graphic DRAM Interface (그래픽 DRAM 인터페이스용 5.4Gb/s 클럭 및 데이터 복원회로)

  • Kim, Young-Ran;Kim, Kyung-Ae;Lee, Seung-Jun;Park, Sung-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.19-24
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    • 2007
  • With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

Bluetooth Synchronous Connection Oriented Link Usage in Networked Control Systems (블루투스 Synchronous Connection Oriented Link를 사용한 네트워크 제어 시스템)

  • Umirov, Ulugbek;Park, Jung-Il
    • Journal of Institute of Control, Robotics and Systems
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    • v.18 no.8
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    • pp.731-737
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    • 2012
  • In this paper the usage of Bluetooth in networked control systems is described. ACL links and commonly used serial port profile built on top of ACL links are analyzed and their problems such as unpredictable latency are discovered. SCO link packet scheduling, latency estimation and setup procedure are examined. SCO link is suggested as proper link for NCS, due to its low latency and low variance. Smith predictor use for latency compensation is described and its impact on control performance is estimated. A number of experiments on DC motor position control are performed and control performance of system utilizing SCO link with and without Smith predictor is proved to be higher than control performance of system utilizing ACL link.

In-plane and out-of-plane bending moments and local stresses in mooring chain links using machine learning technique

  • Lee, Jae-bin;Tayyar, Gokhan Tansel;Choung, Joonmo
    • International Journal of Naval Architecture and Ocean Engineering
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    • v.13 no.1
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    • pp.848-857
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    • 2021
  • This paper proposes an efficient approach based on a machine learning technique to predict the local stresses on mooring chain links. Three-link and multi-link finite element analyses were conducted for a target chain link of D107 with steel grade R4; 24,000 and 8000 analyses were performed, respectively. Two serial Artificial Neural Network (ANN) models based on a deep multi-layer perceptron technique were developed. The first ANN model corresponds to multi-link analyses, where the input neurons were the tension force and angle and the output neurons were the interlink angles. The second ANN model corresponds to the three-link analyses with the input neurons of the tension force, interlink angle, and the local stress positions, and the output neurons of the local stress. The predicted local stresses for the untrained cases were reliable compared to the numerical simulation results.

DESIGN AND ANALYSIS FOR THE SPECIAL SERIAL MANIPULATOR

  • Kim, Woo-Sub;Park, Jae-Hong;Kim, Jung-Ha
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.1396-1401
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    • 2004
  • In recent years, robot has been used widely in industrial field and has been expanded as a result of continous research and development for high-speed and miniaturization. The goal of this paper is to design the special serial manipulator through the understanding of the structure, mobility, and analysis of serial manipulator. Thereafter we control the position and orientation of end-effector with respect to time. In general, a structure of industrial robot consists of several links connected in series by various types of joints. Typically revolute and prismatic joints. The movement of these joints is determined in inverse kinematic analysis. Compared to the complicated structure of parallel and hybrid robot, open loop system retains the characteristic that each link is independent and is controlled easily by AC servomotor that is used to place the robot end-effector toward the accurate point with the desired speed and power while it is operated by position control algorithm. The robot end-effector should trace the given trajectory within the appropriate time. The trajectory of 3D end-effector model made by OpenGL can be displayed on the monitor program simultaneously

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A 1.5 Gbps Transceiver Chipset in 0.13-μm CMOS for Serial Digital Interface

  • Lee, Kyungmin;Kim, Seung-Hoon;Park, Sung Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.4
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    • pp.552-560
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    • 2017
  • This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.