• Proceedings of the KSR Conference
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• 2002.05a
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• pp.530-534
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• 2002

This paper show serial communication method in order to design how to interface between fault tolerant systems with redundancy. Problem has been in the method that fault tolerant system had switched of serial data with common switching device. This problem degrade reliability in itself and total system which is interfaced with that serial communication system. So Arbitration module of serial communication which is suggested in this paper can improve the reliability using voter algorithm which fault is detected passively.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.363-366
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• 2003

We propose the system that automatically adjusts the white balance on display products to a standard value according to several nations. We replace manual or semi-auto method with fully automatic method using windows application program. And we use RS-232C serial interface to communicate PC with display products which we want to adjust white balance. The PC generates patterns for measuring color information and Color Analyzer measures color and brightness. This value is transmitted through RS-232C serial interface to PC. The PC's algorithm analyzes this information and then decides which RGB Gain value is best for optimal white balance. This RGB Gain value is transmitted through RS-232C serial interface to display products. The modified color value is measured again and feed back to PC. This sequence is repeated until optimum white balance is obtained.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.153-158
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• 2010

Most of software developers use the GNU Debugger (GDB) in order to debug code execution. The GDB supports a remote debugging environment through serial communication. However, in embedded systems, the speed is limited in the serial communication. Due to this reason, the serial communication is rarely used for the debugging purpose. To solve this problem, many embedded systems adapt the JTAG and the USB interface. This paper proposes debugging environment via USB-JTAG interface to debug the EISC processor, and introduces how the USB interface works on the GDB and how the JTAG module handles debugging packets.

• ETRI Journal
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• v.34 no.1
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• pp.35-43
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• 2012

This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.622-628
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• 1996

This paper describes a new serial interface system which uses conventional 75 ohm coaxial cable. Typically parallel 25 pin cable and connectors are used to transfer and receive the data between digital systems such as HDVCR, D3 VTR and HDTV Receiver. The coaxial cable is more desirable for consumer product applications and also for studio applications where long signal paths and switching are required. This serial data transfer technique is thoroughly tested and utilied in the data transmission/reception between systems more than 200 feet apart. It is also cost effective because it does not require RF PLL, SCRAMBLING, and NRZI hardware.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.639-641
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• 2002

In this paper, we proposed the multiple access control of RS232C Serial Communications protocol using collision sense method. The communications wires of data transmission and reception are tied together through the buffer each to connect to the multiple communication channels. The hardware interface and control program are designed to build the prototype system and the experimental multiple access communications network is built by multiple PC systems and the transfer completion rate results are shown.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.212-214
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• 2005

The MDDI(Mobile Digital Display Interface) standard is an optimized high-speed serial interconnection technology developed by Qualcomm and supports the VESA(Video Electronics Standard Association). It increases reliability and reduces power consumption in clamshell phones by decreasing the number of wires to interconnect with the LCD display. In this paper, the MDDI host is designed using VHDL and implemented on FPGA. We demonstrates that the MDDI host is connected with S3CA460 LCD controller is designed by Samsung Electronics Co. and display a steal image to the LCD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1814-1819
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• 1996

This paper describes a dnw serial interface system which uses comma free code. Typically parallel 25 pin cable and connectors are used to transfer and receive the data between digital systems such as HDVCR, D3VTR and HDTV Receiver.The coaxial cable is more desirable for consumer product applications and also for studio applications where long signal paths and switching are requeired. This serial data trasfer technique is possible the error detection and the self synchronization, also easy edge insertion for PLL control. It is also cost effective because is does not requeire RF PLL, scrambling, and NRZI hardware.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.