• 대한산업공학회지
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• 제41권6호
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• pp.572-578
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• 2015

Yield prediction is one of the most important issues in semiconductor manufacturing. Especially, for a fast-changing environment of the semiconductor industry, accurate and reliable prediction techniques are required. In this study, we propose a prediction model to predict wafer yield based on virtual metrology process parameters in semiconductor manufacturing. The proposed prediction model addresses imbalance problems frequently encountered in semiconductor processes so as to construct reliable prediction model. The effectiveness and applicability of the proposed procedure was demonstrated through a real data from a leading semiconductor industry in South Korea.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.61-67
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• 2014

Micro-cracks in crystalline silicon wafer often result in wafer breakage in solar wafer manufacturing, and also their existence may lead to electrical failure in post fabrication inspection. Therefore, the reliable detection of micro-cracks is of importance in the photovoltaic industry. In this paper, an experimental method to select optimal parameters in anisotropic diffusion filter is proposed. It can reliably detect micro-cracks by the distinct extension of boundary as well as noise reduction in near-infrared image patterns of micro-cracks. Its performance is verified by experiments of several type cracks machined.

• Industrial Engineering and Management Systems
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• 제4권1호
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• pp.47-53
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• 2005

The efficiency of fabrication (fab) operation is one of the key factors in order for a semiconductor manufacturing company to stay competitive. Optimization of manpower and forecasting manpower needs in a modern fab is an essential part of the future strategic planing and a very important to the operational efficiency. As the semiconductor manufacturing technology has entered the 8-inch wafer era, the complexity of fab operation increases with the increase of wafer size. The wafer handling method has evolved from manual mode in 6-inch wafer fab to semi-automated or fully automated factory in 8-inch and 12-inch wafer fab. The distribution of manpower requirement in each specialty varied as the trend of fab operation goes for downsizing manpower with automation and outsourcing maintenance work. This paper is to study the specialty distribution of manpower from the requirement in a typical 6-inch, 8-inch to 12-inch wafer fab. The human resource planning in today’s fab operation shall consider many factors, which include the stability of technical talents. This empirical study mainly focuses on the human resource planning, the manpower distribution of specialty structure and the forecast model of internal demand/supply in current semiconductor manufacturing company. Considering the market fluctuation with the demand of varied products and the advance in process technology, the study is to design a headcount forecast model based on current manpower planning for direct labour (DL) and indirect labour (IDL) in Taiwan’s fab. The model can be used to forecast the future manpower requirement on each specialty for the strategic planning of human resource to serve the development of the industry.

• 한국신뢰성학회지:신뢰성응용연구
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• 제16권1호
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• pp.26-31
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• 2016

Purpose: The purpose of this study was to investigate the effect of grinding process and thickness on the fracture strength of silicon die used for semiconductor substrate. Method: Silicon wafers with different thickness from $200{\mu}m$ to $50{\mu}m$ were prepared by chemical mechanical polishing (CMP) and dicing before grinding (DBG) process, respectively. Fracture load was measured by point load test for 50 silicon dies per each wafer. Results: Fracture strength at the center area was lower than that at the edge area of the wafer fabricated by DBG process, while random distribution of the fracture strength was observed for the CMPed wafer. Average fracture strength of DBGed specimens was higher than that of the CMPed ones for the same thickness of wafer. Conclusion: DBG process can be more helpful for lowering fracture probability during the semiconductor fabrication process than CMP process.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 2001년도 추계학술대회 논문집
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• 한국산업보건학회지
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• 제25권2호
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• pp.202-210
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• 2015

Objectives: The purpose of this study was to examine clean room(C/R) structure, air conditioning and contamination control systems and to provide basic information for identifying a correlation between the semiconductor work environment and workers' disease. Methods: This study was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. The C/R structure and air conditioning method were investigated using basic engineering data from documentation for C/R construction. Furthermore, contamination parameters such as airborne particles, temperature, humidity, acids, ammonia, organic compounds, and vibration in the C/R were based on the International Technology Roadmap for Semiconductors(ITRS). The properties of contamination control systems and the current status of monitoring of various contaminants in the C/R were investigated. Results: 200 mm and 300 mm wafer fabrication facilities were divided into fab(C/R) and sub fab(Plenum), and fab, clean sub fab and facility sub fab, respectively. Fresh air(FA) is supplied in the plenum or clean sub fab by the outdoor air handling unit system which purifies outdoor air. FA supply or contaminated indoor air ventilation rates in the 200 mm and 300 mm wafer fabrication facilities are approximately 10-25%. Furthermore, semiconductor clean rooms strictly controlled airborne particles(${\leq}1,000{\sharp}/ft^3$), temperature($23{\pm}0.5^{\circ}C$), humidity($45{\pm}5%$), air velocity(0.4 m/s), air change(60-80 cycles/hr), vibration(${\leq}1cm/s^2$), and differential pressure(atmospheric pressure$+1.0-2.5mmH_2O$) through air handling and contamination control systems. In addition, acids, alkali and ozone are managed at less than internal criteria by chemical filters. Conclusions: Semiconductor clean rooms can be a pleasant environment for workers as well as semiconductor devices. However, based on the precautionary principle, it may be necessary to continuously improve semiconductor processes and the work environment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• 한국시뮬레이션학회논문지
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• 제12권3호
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• pp.13-20
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• 2003

Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

• 반도체디스플레이기술학회지
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• 제6권4호
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• pp.49-52
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• 2007

As the minimum feature size decrease, control of contamination by nanoparticles is getting more attention in semiconductor process. Cleaning technology which removes nanoparticles is essential to increase yield. A reference wafer on which particles with known size and number are deposited is needed to evaluate the cleaning process. We simulated particle trajectories in the chamber by using FLUENT. Charged monodisperse particles are generated using SMPS (Scanning Mobility Particle Sizer) and deposited on the wafer by electrostatic force. The Experimental results agreed with the simulation results well. We calculate the particles loss in pipe flow theoretically and compare with the experimental results.