• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.2
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• pp.81-86
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• 2005

This paper proposes a non-destructive ESPI technique to quantitatively evaluate defects inside a semiconductor package. The inspection system consists of the ESPI system, a thermal loading system and an adiabatic chamber. The technique is high feasibility for non-destructive testing of a semiconductor and overcomes the weaknesses of previous techniques, such as time-consumption and difficult quantitative evaluation. Most defects are classified as delamination defects, resulting from the insufficient adhesive strength between layers and from non-homogeneous heat spread. Ninety percent of the tested samples had delamination defects which originated at the corner of the chip and nay be related to heat spread design.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.6
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• pp.694-699
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• 2012

In this paper, semiconductor package inspection results using white light interferometer with large F.O.V., in order to apply semiconductor product inspection process, are shown. Experimental 3D data repeatability test results for the same special bumps of each substrate are shown. Experimental 3D data repeatability test results for all the bumps in each substrate are also shown. Semiconductor package inspection using white light interferometer with large F.O.V. is very important for the fast 3D data inspection in semiconductor product inspection process. This paper is surely helpful for the development of in-line type fast 3D data inspection machine.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.05a
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• pp.26-36
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• 1999

• Journal of the Korea Society for Simulation
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• v.19 no.1
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• pp.1-11
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• 2010

K company produces semiconductor package products under the make-to-order policy to supply for domestic and foreign semiconductor manufacturing companies. Its production process is a machine-paced assembly line type, which consists of die sawing, assembly, and test. This paper suggests three plans to increase process throughput based on the process analysis of K company and evaluates them via a simulation model using a real data collected. The three plans are line balancing by adding machines to the bottleneck process, product group scheduling, and reallocation of the operators in non-bottleneck processes. The evaluation result shows the highest daily throughput increase of 17.3% with an effect of 2.8% reduction of due date violation when the three plans are applied together. Payback period for the mixed application of the three plans is obtained as 1.37 years.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.35-39
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• 2023

ESG (Environment, Social, Governance) has become a major guideline for many companies to improve corporate value and enable sustainable management. Among them, the environment requires a technological approach. This is because technological solutions are needed to reduce or prevent environmental pollution and save energy. Semiconductor package technology has been developed to better satisfy the essential roles of semiconductor packaging: chip protection, electrical/mechanical connection, and heat dissipation. Accordingly, technologies have been developed to improve heat dissipation effect, improve electrical/mechanical properties, improve chip protection reliability, stacking and miniaturization, and reduce costs. Among them, heat dissipation technology increases thermal efficiency and reduces energy consumption for cooling. Also, technology to improve electrical characteristics has had an impact on the environment by reducing energy consumption. Technologies that recycling or reducing material consumption reduce environmental pollution. And technologies that replace environmentally harmful substances contribute to environmental improvement, in particular. In this paper, I summarize trends in semiconductor package technologies to prevent pollution and improve environment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.53-56
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• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.6
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• pp.506-509
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• 2005

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.158-162
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• 2002

This paper presents a novel 3-phase IGBT module called the SPM (Smart Power Module). This is a new design developed to provide a very compact, low cost, high performance and reliable motor drive system. Several distinct design concepts were used to achieve the highly integrated functionality in a new cost-effective small package. An overall description to the SPM is given and actual application issues such as electrical characteristics, circuit configurations, thermal performance and power ratings are discussed

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.