• 대한산업공학회지
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• 제41권3호
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• pp.267-274
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• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• 한국화재소방학회논문지
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• 제10권2호
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• 한국공작기계학회논문집
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• 제18권1호
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• pp.1-12
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• 2009

Presently, the semiconductor industry has the chronic problem. In the semiconductor industry, it has the semiconductor wafer, a package, the optical filter cut by using the saw blade, the mold, a laser etc. The cutting technique has the difficulty due to the rising of the production cost by the wearing of mold, the poor quality problem due to generated heat at the moment of cutting procedure and curve cutting etc. The goal of this time of national research and development project is develop the apparatus for solving the problem that the existing cutting technique has. The technology is so called waterjet abrasive method. This technology will be mainly applied to cut a semiconductor package and a wafer. Two important things to be considered are ripple effect(in other words, the scale of a market) and simplicity of an application.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.99.4-99
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• 1998

• 한국산학기술학회논문지
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• 제22권1호
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• pp.327-332
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• 2021

패키지레벨에서 반도체의 신뢰성 검사는 테스트 소켓에 반도체 칩 패키지를 탑재시킨 상태에서 테스트가 진행되며, 테스트 소켓은 기본적으로 반도체 칩 패키지의 형태에 따라서 그 모양이 결정되는 것이 일반적이다. 또한, 반도체 칩 패키지의 리드와 소켓 리드의 기계적인 접촉에 의해 테스트 장비와 연결하는 매개체의 역할을 하며, 신호전달 과정에서 신호의 손실을 최소화하여 반도체에 검사신호를 잘 전달할 수 있도록 하는 기능이 핵심이다. 본 연구에서는 이웃하고 있는 전기 전달 경로의 상호 영향성을 검사 할 수 있는 기술을 적용함으로써 수명 검사와 정밀 측정뿐만 아니라 이웃하고 있는 전기 전달 경로의 구조를 포함하여 단 한 번의 접촉을 통해 100개미만의 실리콘 테스트 소켓의 합선 테스트가 가능하도록 개발하였다. 개발된 장치의 테스트 결과 99%이상의 테스트 정밀도와 0.66이하의 동시 검사속도 특성을 나타내었다.

• 비파괴검사학회지
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• 제21권6호
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• pp.598-606
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• 2001

최근 전자장치의 고기능화에 따라서 반도체 장치의 고집적화는 물론 반도체 패키지의 박형화 추세에 있다. 이러한 반도체가 장치에 실장된 후에도 안정된 성능을 발휘할 수 있는지 여부에 대한 신뢰성을 보장하기 위해 조립 완료된 반도체 패키지에 대한 preconditioning 시험을 수행하게 된다. 또한 preconditioning 시험 전후에 초음파 주사 현미경을 이용한 검사를 실시함으로써 반도체 패키지에 대한 들뜸이나 패키지 크랙과 같은 내부 결함의 존재 여부를 알아보게 된다. 본 논문에서는 반도체 내부의 결함 유무를 효과적으로 검사할 수 있는 초음파를 이용한 신뢰성 평가 방법과 절차를 제시하고, preconditioning 시험 과정에서 수행되는 시험법을 통해 패키지 내부 결함을 야기하는 가장 중요한 요인이라 할 수 있는 수분에 의한 고장 메커니즘을 분명히 함으로써 반도체 패키지에 대한 일련의 고장 분석 및 신뢰성 평가 방법을 정립하고자 하였다.

• 반도체디스플레이기술학회지
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• 제18권1호
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• pp.65-69
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• 2019

The cure properties of ethoxysilyl diglycidyl isocyanurate(Ethoxysilyl-DGIC) and ethylsilyl diglycidyl isocyanurate (Ethylsilyl-DGIC) epoxy resin systems with a phenol novolac hardener were investigated for anticipating fan out-wafer level package(FO-WLP) applications, comparing with ethoxysilyl diglycidyl ether of bisphenol-A(Ethoxysilyl-DGEBA) epoxy resin systems. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The isocyanurate type epoxy resin systems represented the higher cure conversion rates comparing with bisphenol-A type epoxy resin systems. The Ethoxysilyl-DGIC epoxy resin system showed the highest cure conversion rates than Ethylsilyl-DGIC and Ethoxysilyl-DGEBA epoxy resin systems. It can be figured out by kinetic parameter analysis that the highest conversion rates of Ethoxysilyl-DGIC epoxy resin system are caused by higher collision frequency factor. However, the cure conversion rate increases of the Ethylsilyl-DGEBA comparing with Ethoxysilyl-DGEBA are due to the lower activation energy of Ethylsilyl-DGIC. These higher cure conversion rates in the isocyanurate type epoxy resin systems could be explained by the improvements of reaction molecule movements according to the compact structure of isocyanurate epoxy resin.

• 한국공작기계학회논문집
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• 제17권3호
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

• 전자통신동향분석
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• 제35권2호
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• pp.89-103
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 전자통신동향분석
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• 제35권2호
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• pp.120-136
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.