• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Korean Journal of Optics and Photonics
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• v.15 no.4
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• pp.349-354
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• 2004

As a transmitter sub-assembly in the XFP(10 Gb/s Small Form Factor Pluggable) transceiver module, a transmitter optical sub-assembly(TOSA) is designed, fabricated and characterized in view of electrical and thermal performances. For a low-cost and compact packaging TOSA, the bias-tee and the matching resistor are monolithically integrated on the AlN sub-mount and a newly designed coplanar waveguide is drawn in the TO-stem. All optoelectronic components packaged in the TOSA are modeled by the equivalent circuit, which helps to improve and characterize the TOSA performance. The fabricated TOSA shows the -3㏈ bandwidth as high as 11 GHz at an elevated temperature of 85$^{\circ}C$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.29-33
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• 2000

MEMS, Micro Electro-Mechanical Systems, present one of the greatest advanced packaging challenges of the next decade. Historically hybrid technology, generally thick film, provided sensors and actuators while integrated circuit technologies provided the microelectronics for interpretation and control of the sensor input and actuator output. Brought together in MEMS these technical fields create new opportunities for miniaturization and performance. Integrated circuit processing technologies combined with hybrid design systems yield innovative sensors and actuators for a variety of applications from single crystal silicon wafers. MEMS packages, far more simple in principle than today's electronic packages, provide only physical protection to the devices they house. However, they cannot interfere with the function of the devices and often must actually facilitate the performance of the device. For example, a pressure transducer may need to be open to atmospheric pressure on one side of the detector yet protected from contamination and blockage. Similarly, an optical device requires protection from contamination without optical attenuation or distortion being introduced. Despite impediments such as package standardization and complexity, MEMS markets expect to double by 2003 to more than ＄9 billion, largely driven by micro-fluidic applications in the medical arena. Like the semiconductor industry before it. MEMS present many diverse demands on the advanced packaging engineering community. With focused effort, particularly on standards and packaging process efficiency. MEMS may offer the greatest opportunity for technical advancement as well as profitability in advanced packaging in the first decade of the 21st century! This paper explores MEMS packaging opportunities and reviews specific technical challenges to be met.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.26-29
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• 2004

High density plasma fluorinated silicate glass (HDP FSG) is used as a gap fill film for metal-to-metal space because of many advantages. However, FSG films can cause critical problems such as bonding issue of top metal at package, metal contamination, metal peel-off, and so on. It is known that these problems are caused by fluorine penetration out of FSG film. To prevent it, FSG capping layers such like SRO (Silicon Rich Oxide) are needed. In this study, their characteristics and a capability to block fluorine penetration for various FSG capping layers are investigated. Normal stress and High stress due to denser film. While heat treatment to PETEOS caused lower blocking against fluorine penetration, it had insignificant effect on SiN. Compared with other layers, SRO using ARC chamber and SiN were shown a better performance to block fluorine penetration.

• 한국전산유체공학회:학술대회논문집
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• 2011.05a
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.5
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• pp.515-520
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• 2004

We report on the development of a Piezoelectric valvc that is designed to have a high reliability for fluid control systems, such as mass flow control, transportation and chemical analysis. The valve was fabricated using a MCA(multilayer ceramic actuator), which has a low consumption power, high resolution and accurate control. The fabricated valve is composed of MCA, a valve actuator die and an seat die. The design of the actuator dic was done by FEM(finite element method) modeling, respectively. And, the valve seat die with 6 trenches was made. and the actuator die, which possible to optimize control to MCA, was fabricated. After Si-wafer direct bonding between the seat die and the actuator die, MCA was also anodic bonded to the scat/actuator die structure. PDMS(poly dimethylsiloxane) sealing pad was fabricated to minimize a leak-rate. It was also bonded to scat die and stainless steel package. The flow rate was 9.13 sccm at a supplied voltage of 100 V with a 50 % duty ratio and non-linearity was 2.24 % FS. From these results, the fabricated MCA valve is suitable for a variety of flow control equipments, a medical bio-system, semiconductor fabrication process, automobile and air transportation industry with low cost, batch recess and mass production.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.2
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• pp.133-138
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• 2005

The deformation of sheet metal due to the residual stress during blanking or piercing process, is numerically simulated by means of a commercial finite element code. Two dimensional plain strain problem is solved and then its result is applied to the deformation analysis of the lead frame. The plain strain element is applied to the 2D problem to observe the Von Mises equivalent stress concentration at the both shearing edges. As the punch penetrates into the sheet material, the stress concentration generated on both edges is getting increased to be the shearing surface. The limits of the punching depth applied to the simulation is 16% and 24% of the sheet thickness for the plain strain element and the hexahedral element, respectively. The hexahedral element and the limit of punching depth were applied to the deformation analysis of the lead frame for the blanking process. The FEM results for the lead deformation were very good agreement with the experimental ones. This paper shows that the coarse mesh has enabled to analyze the lead deformation generated due to the blanking mechanism. This simple approach to save the calculation time will be very effective to the design of the blanking tools in industries.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.733-740
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• 2014

A resistive micro Pirani gauge using amorphous silicon (a-Si) thin membrane is proposed. The proposed Pirani gauge can be easily integrated with the other process-compatible membrane-type sensors, and can be applicable for in-situ vacuum monitoring inside the vacuum package without an additional process. The vacuum level is measured by the resistance changes of the membrane using the low noise correlated double sampling (CDS) capacitive trans-impedance amplifier (CTIA). The measured vacuum range of the Pirani gauge is 0.1 to 10 Torr. The sensitivity and non-linearity are measured to be 78 mV / Torr and 0.5% in the pressure range of 0.1 to 10 Torr. The output noise level is measured to be $268{\mu}V_{rms}$ in 0.5 Hz to 50 Hz, which is 41.2% smaller than conventional CTIA.

• Journal of electromagnetic engineering and science
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• v.13 no.4
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• pp.233-239
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• 2013

This paper proposes an accurate approach for predicting transferred power from a noise source to integrated circuits based on the characteristics of the power transfer network. A power delivery trace on a package and a printed circuit board are designed to transmit power from an external source to integrated circuits. The power is demonstrated between an injection terminal on the edge of the printed circuit board and integrated circuits, and the power transfer function of the power distribution network is derived. A two-tier calibration is applied to the test, and scattering parameters of the network are measured for the calculation of the power transfer function. After testing to obtain the indispensable parameters, the real received and tolerable power of the integrated circuits can be easily achieved. Our proposed estimation method is an enhancement of the existing the International Electrotechnical Commission standard for precise prediction of the electromagnetic immunity of integrated circuits.

• Journal of Information Display
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• v.2 no.4
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• pp.34-38
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• 2001

We suggested new PDP packaging technology using the direct joint method, which does not need an exhausting hole and tube. The advantages of this method are simple process, short process time and time panel package. To packaging, we drew the seal line of glass frit by dispenser followed by forming the lump, which provide pumping-out path during the packaging process. And, we have performed a pretreatment of glass frit to reduce the out-gases. After which, both front and rear glass plates were aligned and loaded into vacuum packaging chamber. The 4-inch monochrome AC-PDP was successfully packaged and fully emitted with brightness of 1000 $cd/m^2$. Also, glass frit properties for pretreatment condition was investigated by AES and SEM analyses.