• Title/Summary/Keyword: Semiconductor package

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Prediction of field failure rate using data mining in the Automotive semiconductor (데이터 마이닝 기법을 이용한 차량용 반도체의 불량률 예측 연구)

  • Yun, Gyungsik;Jung, Hee-Won;Park, Seungbum
    • Journal of Technology Innovation
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    • v.26 no.3
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    • pp.37-68
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    • 2018
  • Since the 20th century, automobiles, which are the most common means of transportation, have been evolving as the use of electronic control devices and automotive semiconductors increases dramatically. Automotive semiconductors are a key component in automotive electronic control devices and are used to provide stability, efficiency of fuel use, and stability of operation to consumers. For example, automotive semiconductors include engines control, technologies for managing electric motors, transmission control units, hybrid vehicle control, start/stop systems, electronic motor control, automotive radar and LIDAR, smart head lamps, head-up displays, lane keeping systems. As such, semiconductors are being applied to almost all electronic control devices that make up an automobile, and they are creating more effects than simply combining mechanical devices. Since automotive semiconductors have a high data rate basically, a microprocessor unit is being used instead of a micro control unit. For example, semiconductors based on ARM processors are being used in telematics, audio/video multi-medias and navigation. Automotive semiconductors require characteristics such as high reliability, durability and long-term supply, considering the period of use of the automobile for more than 10 years. The reliability of automotive semiconductors is directly linked to the safety of automobiles. The semiconductor industry uses JEDEC and AEC standards to evaluate the reliability of automotive semiconductors. In addition, the life expectancy of the product is estimated at the early stage of development and at the early stage of mass production by using the reliability test method and results that are presented as standard in the automobile industry. However, there are limitations in predicting the failure rate caused by various parameters such as customer's various conditions of use and usage time. To overcome these limitations, much research has been done in academia and industry. Among them, researches using data mining techniques have been carried out in many semiconductor fields, but application and research on automotive semiconductors have not yet been studied. In this regard, this study investigates the relationship between data generated during semiconductor assembly and package test process by using data mining technique, and uses data mining technique suitable for predicting potential failure rate using customer bad data.

Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals

  • Gutmann, R.J.;Zeng, A.Y.;Devarajan, S.;Lu, J.Q.;Rose, K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.196-203
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    • 2004
  • A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

Atomistic simulation of surface passivated wurtzite nanowires: electronic bandstructure and optical emission

  • Chimalgi, Vinay U.;Nishat, Md Rezaul Karim;Yalavarthi, Krishna K.;Ahmed, Shaikh S.
    • Advances in nano research
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    • v.2 no.3
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    • pp.157-172
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    • 2014
  • The three-dimensional Nano-Electronic Modeling toolkit (NEMO 3-D) is an open source software package that allows the atomistic calculation of single-particle electronic states and optical response of various semiconductor structures including bulk materials, quantum dots, impurities, quantum wires, quantum wells and nanocrystals containing millions of atoms. This paper, first, describes a software module introduced in the NEMO 3-D toolkit for the calculation of electronic bandstructure and interband optical transitions in nanowires having wurtzite crystal symmetry. The energetics (Hamiltonian) of the quantum system under study is described via the tight-binding (TB) formalism (including $sp^3$, $sp^3s^*$ and $sp^3d^5s^*$ models as appropriate). Emphasis has been given in the treatment of surface atoms that, if left unpassivated, can lead to the creation of energy states within the bandgap of the sample. Furthermore, the developed software has been validated via the calculation of: a) modulation of the energy bandgap and the effective masses in [0001] oriented wurtzite nanowires as compared to the experimentally reported values in bulk structures, and b) the localization of wavefunctions and the optical anisotropy in GaN/AlN disk-in-wire nanowires.

Wafer-Level Packaged MEMS Resonators with a Highly Vacuum-Sensitive Quality Factor

  • Kang, Seok Jin;Moon, Young Soon;Son, Won Ho;Choi, Sie Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.632-639
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    • 2014
  • Mechanical stress and the vacuum level are the two main factors dominating the quality factor of a resonator operated in the vacuum range 1 mTorr to 10 Torr. This means that if the quality factor of a resonator is very insensitive to the mechanical stress in the vacuum range, it is sensitive to mainly the ambient vacuum level. In this paper, a wafer-level packaged MEMS resonator with a highly vacuum-sensitive quality factor is presented. The proposed device is characterized by a package with out-of-plane symmetry and a suspending structure with only a single anchor. Out-of-plane symmetry helps prevent deformation of the packaged device due to thermal mismatch, and a single-clamped structure facilitates constraint-free displacement. As a result, the proposed device is very insensitive to mechanical stress and is sensitive to mainly the ambient vacuum level. The average quality factors of the devices packaged under pressures of 50, 100, and 200 mTorr were 4987, 3415, and 2127, respectively. The results demonstrated the high controllability of the quality factor by vacuum adjustment. The mechanical robustness of the quality factor was confirmed by comparing the quality factors before and after high-temperature storage. Furthermore, through more than 50 days of monitoring, the stability of the quality factor was also certified.

MAGFET Hybrid IC with Frequency Output (주파수 출력을 갖는 MAGFET Hybrid IC)

  • Kim, Si-Hon;Lee, Cheol-Woo;Nam, Tae-Chul
    • Journal of Sensor Science and Technology
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    • v.6 no.3
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    • pp.194-199
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    • 1997
  • When voltage or current gets out of the magnetic sensor as it is, we have often faced the problems such as introduction of noise and loss of voltage. In order to reduce these problems, a 2 drain MAGFET operating in the saturation region and fabricated by CMOS process, the system of I/V converter, VCO with operational amplifier, and V/F conversion circuits with Schmitt Trigger are designed and fabricated in one package. The absolute sensitivity of magnetic sensor shows 1.9 V/T and the product sensitivity is $3.2{\times}10^{4}\;V/A{\cdot}T$. The characteristic of V/F conversion is very stabilized and has the value of 190 kHz/T.

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A numerical deformation analysis of micro elements by stamping orders (스탬핑 순서가 미치는 미세요소 변형 수치해석)

  • Lee, Chang-Hee;Kim, Yong-Yun
    • Journal of the Korean Society for Precision Engineering
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    • v.22 no.12 s.177
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    • pp.156-162
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    • 2005
  • In this paper, we study the mechanism of lead deformation by numerically simulating the stamping process by means of a commercial finite element code. It is very important to analyze effects that the lead shape makes on the lead deformation, because the lead shape is often modified in order to minimize the deformation or to increase the buckling critical load of the punch. Therefore the stamping process, first, numerically simulated by considering as a quasi-static problem. Second, the effect on the lead deformation due to the lead shape variation, a linear lead geometry and a bent lead, was numerically analyzed and discussed. Finally, the punching order was optimized fur multi-lead generating stamping process. The results show that the bent lead is little bit more shifted than the linear lead after the punching process. But the bent lead is vertically less deformed than the linear lead. The punching order to successively generate the lead is good to keep the lead space uniform. The results will be very effectively applied for the design of the blanking or punching dies in industry.

Pattern Partitioning and Decision Method in the Semiconductor Chip Marking Inspection (반도체 부품 마크 미세 결함 검사를 위한 패턴 영역 분할 및 인식 방법)

  • Zhang, Yuting;Lee, Jung-Seob;Joo, Hyo-Nam;Kim, Joon-Seek
    • Journal of Institute of Control, Robotics and Systems
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    • v.16 no.9
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    • pp.913-917
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    • 2010
  • To inspect the defects of printed markings on the surface of IC package, the OCV (Optical Character Verification) method based on NCC (Normalized Correlation Coefficient) pattern matching is widely used. In order to detect the micro pattern defects appearing on the small portion of the markings, a Partitioned NCC pattern matching method was proposed to overcome the limitation of the NCC pattern matching. In this method, the reference pattern is first partitioned into several blocks and the NCC values are computed and are combined in these small partitioned blocks, rather than just using the NCC value for the whole reference pattern. In this paper, we proposed a method to decide the proper number of partition blocks and a method to inspect and combine the NCC values of each partitioned block to identify the defective markings.

A Study on the Simulation of the Resolution for Ink-Jet Printing (잉크젯 프린팅에서 해상력에 관한 컴퓨터 시뮬레이션 연구)

  • Lee, Ji-Eun;Youn, Jong-Tae;Koo, Chul-Whoi
    • Journal of the Korean Graphic Arts Communication Society
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    • v.28 no.1
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    • pp.51-63
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    • 2010
  • Ink-jet is part of the non impact printing that shooting the ink drop from the nozzle to paper. It is very silence and express good color. There are two types of printing that continuous and drop on demand. But drop on demand process is becoming the mainstream. these days, LCD, PDP is passed more than semiconductor industry. And we expect organic EL, FED as a next display. But product equipment, main component and technology have a gap between an advanced country and us nevertheless physical development. Expecially, previous process part is depended on imports. Ink-jet printing technology that there isn't complicated photo lithography process is attracted, so ink-jet printing resolution is more embossed. But there were not many of ink-jet resolution thesis but ink-jet head or nozzle. Because, to out of the ink from the nozzle is unseeable and hard to experiment. Therefore this thesis was experimented and simulated how can ink-jet printer improved resolution by flow-3d simulation package program.

Modeling and Prediction of Electromagnetic Immunity for Integrated Circuits

  • Pu, Bo;Kim, Taeho;Kim, SungJun;Kim, SoYoung;Nah, Wansoo
    • Journal of electromagnetic engineering and science
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    • v.13 no.1
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    • pp.54-61
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    • 2013
  • An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.

A Low-Power Single Chip Li-Ion Battery Protection IC

  • Lee, Seunghyeong;Jeong, Yongjae;Song, Yungwi;Kim, Jongsun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.4
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    • pp.445-453
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    • 2015
  • A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a $0.18-{\mu}m$ CMOS process occupies an area of $750{\mu}m{\times}610{\mu}m$. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes $3{\mu}A$ under normal operating conditions and $0.45{\mu}A$ under standby mode.